Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Patent
1994-02-25
1996-07-30
Carroll, J.
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
257637, 437231, 437235, H01L 2358
Patent
active
055414451
DESCRIPTION:
BRIEF SUMMARY
This invention relates to a method of passivating a semiconductor device, and a semiconductor device passivated thereby.
Typical semiconductor devices consist of a large number of active components formed on a substrate and include one or two levels of polysilicon, polycide, silicide or a combination of thereof, as well as one, two or more levels of interconnect layers insulated by various dielectrics.
Moisture and ions of various types can have very important negative effects on the performance and reliability of such devices.
CMOS transistors show threshold voltage instabilities when sodium, Na.sup.+, lithium, Li.sup.+, potassium, K.sup.+, hydrogen, H.sup.+, hydronium, H.sub.3 O.sup.+, and hydroxyl, OH.sup.-, ions are allowed to approach the gate oxide area. Hydrogen, hydronium and hydroxyl ions originate from moisture ionization.
Interconnect materials, such as aluminum alloys and titanium-based refractory metals and compounds corrode when electrically polarized and exposed to moisture. These galvanic reactions occur faster when catalyst ions, such as chlorine, Cl.sup.-, are present in trace levels and when elements like copper are used in the aluminum alloy.
Dielectrics are electrically affected by moisture. For example, bulk resistivity reduction, electrical polarization, hot electron effects, and slow trapping degradation. They are also affected mechanically in that they tend to acquire a compressive stress as they absorb moisture. They can also be chemically attacked, particularly when alloyed with boron and phosphorus. Decomposition to boric and phosphoric acids can result and initiate corrosion of surrounding interconnect materials.
In order to prevent moisture build-up and ion penetration in the device, it is known to form a passivation layer on the surface of the device. This is usually patterned to permit the opening of the bond pads to which bond wires are connected. The passivation layer also prevents conductive particles and scratches from shorting top interconnects.
The passivation layer can be deposited from silicon, oxygen, nitrogen, phosphorus and/or a gas containing another metallic element by, for example, atmospheric pressure chemical vapour deposition (APCVD), low pressure chemical vapour deposition (LPCVD), plasma enhanced chemical vapour deposition (PECVD), laser assisted chemical vapour deposition, LACVD, photo assisted chemical vapour deposition (PACVD), or electron cyclotron resonance chemical vapour deposition (ECRCVD). This layer can be deposited from silicon, and/or silicon nitride, and/or silicon oxide, and/or silicon oxinitride targets, with or without oxygen, nitrogen or any other reactive gas, by sputtering, reactive sputtering, biased sputtering, or reactive biased sputtering. It can also be deposited by any combination of these techniques.
The deposited film consists of silicon oxide, which can be alloyed with phosphorus or other metallic elements, silicon nitride, silicon oxinitride, or combination thereof.
Since the passivation layer is deposited from the vapour phase or by sputtering, the surface coverage is strongly affected by the exposed solid angle of the surface to cover. The upper topography, which is characterized by a large exposed solid angle receives more passivation material, and thus produces a thicker passivation layer than the recessed regions with only small solid angle exposed to the vapour from which the passivation layer grows. The net result is a passivation surface coverage that varies with the underlying topography and has many seems, gaps, voids and other weak points.
Water vapour molecules can diffuse in the passivation layer at a rate which is a function of its diffusion constant, D, in the passivation material. The time, t, needed for water to diffuse through the passivation material is proportional to the square of the passivation layer thickness .delta..sup.2 and inversely proportional to the diffusion constant. This means that, at any temperature and for any concentration of moisture in the device area, a thick passivation layer .delta..su
REFERENCES:
patent: 4775550 (1988-10-01), Chu et al.
patent: 4965226 (1990-10-01), Gootzen et al.
patent: 5037777 (1991-08-01), Mele et al.
patent: 5135608 (1992-08-01), Okutani
patent: 5202275 (1993-04-01), Sugiura et al.
patent: 5270267 (1993-12-01), Quellet
Carroll J.
Mitel Corporation
LandOfFree
High performance passivation for semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High performance passivation for semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance passivation for semiconductor devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1661286