Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1997-06-11
2003-10-28
Paladini, Albert W. (Department: 2125)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000, C174S261000, C361S795000, C257S700000
Reexamination Certificate
active
06639155
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to electronic packages and, more particularly, to the fabrication of an improved module which serves as an interconnecting platform between an integrated circuit chip and a card.
2. Description of the Prior Art
One standard type of electronic package involves three distinct levels of components involving an integrated circuit package commonly known as a chip, a module which serves as an interconnecting platform between one or more chips and a card, and the card which provides electronic communication along a multiplicity of modules mounted thereon. Elimination of one of the above three distinct levels of packaging has been long standing goal of those skilled in the art of designing and producing electronic packages. The advantages of eliminating one of the levels of packaging are many, but the prime motivations are cost reduction, improved electrical performance, and superior overall reliability of the package.
One prior approach of module manufacturers has been to make the module component large enough to be able to package the entire function of the computer in one module. However, the performance of the very large metallized ceramic modules produced suffered due to the high dielectric constant of the ceramic material and the manufacturing costs were very high with this approach. More specifically, as the size of the module was increased, the time that it took for electrical signals to pass between the outer extremities of the module became too extended. This is due to the high dielectric constant of the ceramic material. Module fabricators cannot easily change their module material set to incorporate different materials with lower dielectric coefficients than the conventionally used ceramics since their existing base manufacturing processes have been customized to handle and process ceramic materials.
Card fabricators have attempted to produce laminated multilayer multiple chip carriers (modules) which use standard printed circuit board materials and processes. But these packages cannot support very high density chips, nor are they compatible with all of the various conventional chip attachment techniques. Other card manufacturers have made great strides in the direct mounting of chips onto their card products. Indeed, use of materials such as polyimide and Teflon™ have allowed the card manufacturers to produce chip carriers (modules) which have low dielectric constants. However, the card and board manufacturers are limited to relatively low wiring densities due to the nature of the processes that are normally run in a board fabricator, and the general lack of contamination control required to produce circuit lines and spaces with high yields in the order of 25 microns or less that are required to wire-out the current generation of high density chips. It thus has been unattractive from a cost standpoint for a board fabricator to make the significant financial investment that would be needed to produce large multi-chip modules which could package an entire computer or computer function.
One alternative approach has been to use a low thermal expansion and low dielectric constant material such as silica-filled polytetrafluoroethylene (PTFE). To overcome process problems, a spray coating of polyimide is used to protect the silica-filled PTFE from process chemicals in the fabrication of an organic chip carrier, as proposed in commonly assigned U.S. patent application Ser. No. 08/790,245, filed Jan. 28, 1997.
U.S. Pat. No. 4,847,146 to Yeh et al. describes a printed wiring board upon which a ceramic leadless chip carrier is mounted. The printed wiring board has an expansion layer as a surface layer bonded to an underlying rigid support layer, which is a multi-layer laminated board, by an intervening adhesive layer. The adhesive layer is not bonded to the expansion layer at the area beneath the chip carrier by providing a polytetrafluoroethylene layer between the expansion layer and the adhesive layer at that area. The polytetrafluoroethylene layer is thereby used to produce an unbonded area which prevents adhesion of the support layer to the expansion layer so that the expansion layer is free to expand and contract with the chip carrier irrespective of the remainder of the printed wiring board.
U.S. Pat. No. 4,849,284 to Arthur et al. describes a ceramic filled fluoropolymer-based electrical substrate material suitable for forming rigid printed wiring board substrate materials and integrated circuit chip carriers. Conductive patterns and circuits are provided on individual ceramic filled fluoropolymer substrate layers to provide circuit substrates used in the construction of a multilayer board, and plated through holes interconnect selected circuit patterns in a known manner. The circuit substrate also can be used on the top surface of a leadless chip carrier package.
U.S. Pat. No. 5,194,713 to Egitto et al. describes removal of excimer laser debris in a method of fabricating a microelectronic circuit package having a glass fiber reinforced perfluorocarbon polymer dielectric.
Other conventional chip carrier and module constructions are described, e.g., in U.S. Pat. No. 4,965,702 to Lott et al., U.S. Pat. No. 5,249,101 to Frey et al., U.S. Pat. No. 5,264,664 to McAllister et al.
SUMMARY OF THE INVENTION
The present invention provides a packaging platform for interconnecting integrated circuit chips and cards, in which the platform is a circuitized fluoropolymer-based laminate carrier including high purity fluoropolymer protective barriers on its surfaces.
More particularly, a skived polytetrafluoroethylene layer is formed on each of the upper and lower outermost major surfaces of a fluoropolymer-based laminate carrier structure to protect ceramic-containing fluoropolymer dielectric layers in the polymer-based laminate structure against absorption of process chemicals, such as photoresist stripping chemicals, encountered during fabrication of the carrier.
In one preferred embodiment, the present invention uses a polytetrafluoroethylene (PTFE) layer that is free and devoid of ceramic constituents, such as silica, as an outer covering layer to protect ceramic-containing polytetrafluoroethylene dielectric layers in the laminate carrier against attack by process chemicals, such as resist strippers.
Also, a metal capping technique is used on the vias and through holes that does not require precious metal on both the partially completed circuit board and the foil, but instead merely on the partially completed circuit board. This simplifies processing by eliminating one plating step, and eliminates the need for precise alignment.
Because of the materials and processes selected to manufacture the high performance packaging carrier platform used in this invention, there is complete flexibility in the types of chips which can be mounted on the electronic package: C
4
flip chip, low temperature flip chip, or wire bond. In addition, ease of manufactureability and processing costs have been considered when laying out the packaging platform approach. Also, the fine line circuitry capability of the metallized ceramic modules produced by this invention is sufficient to wire-out the current generation of high density chips. Additionally, the elimination of one level of packaging becomes an achievable high yield manufacturing commodity. Also, the implementation of this invention does not require the outlay of large amounts of capital in order to set up a manufacturing line capable of forming and using the carrier platform of the invention in electronic packaging.
REFERENCES:
patent: 4783359 (1988-11-01), Fleischer et al.
patent: 4830704 (1989-05-01), Voss et al.
patent: 4847146 (1989-07-01), Yeh et al.
patent: 4849284 (1989-07-01), Arthur et al.
patent: 4965702 (1990-10-01), Lott et al.
patent: 5038996 (1991-08-01), Wilcox et al.
patent: 5194713 (1993-03-01), Egitto et al.
patent: 5229550 (1993-07-01), Bindra et al.
patent: 5249101 (1993-09-01), Frey et al.
patent: 5264664 (1993-11-01), McAllister et al
Bupp James R.
Farquhar Donald S.
Jimarez Lisa J.
McGuireWoods LLP
Paladini Albert W.
Schiesser William E.
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