High performance output buffer with ESD protection

Details High performance output buffer with ESD protection High performance output buffer with ESD protection

1999-11-24

2002-08-13

Huynh, Kim (Department: 2839)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S056000, C327S437000, C326S083000

Reexamination Certificate

active

06433983

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to output buffers, and more particularly to high performance output buffers with built-in ESD protection. The term output buffer, as used herein, refers to all circuits that buffer electrical signals including amplifying and non-amplifying circuits or devices.
Moore's Law, which is named after Gordon Moore, the founder of Intel Corporation, states that the speed and density of computers will double every 18-24 months. For the most part, Moore's Law has held true since the early days of the microprocessor, and is predicted to do so for at least another twenty years.
A corollary to Moore's Law is that the size of the transistors used on an integrated circuit must shrink by a factor of two every 18-24 months. Until recently, this was accomplished by simply scaling bulk MOSFET devices. However, as the transistor channel lengths scale below about 0.25 um, a number of transistor effects begin to degrade the transistor's characteristics. Some of these effects include short-channel effects, gate resistance effects, channel profiling effects and other effects. It has been found that reducing the power supply voltage can reduce some of these effects. However, reducing the power supply voltage can also severely impact the performance of the MOSFET devices.
One approach for overcoming many of these limitations is to use a Silicon-On-Insulator (SOI) substrate. SOI has significant advantages over bulk CMOS including lower power consumption, lower leakage current, lower capacitance, good sub-threshold IV characteristics, lower soft error rates for both alpha particles and cosmic rays, etc. These advantages make SOI an ideal technology for high performance, low voltage applications.
Another advantage of SOI is that the body of each transistor can be separately controlled. As discussed in “High Speed SOI Buffer Circuit with the Efficient Connection of Subsidiary MOSFET's for Dynamic Threshold Control”, Lee et al., Proceedings 1997 IEEE International SOI Conference, October 1997, page 152, this allows the threshold voltage of each transistor to be dynamically controlled, particularly at low supply voltages. Dynamically adjusting the threshold voltages can significantly increase the performance that can be achieved at low supply voltages.
One of the challenges for providing viable SOI devices is the need to provide adequate electrostatic discharge (ESD) protection. ESD is an increasingly significant problem in integrated circuit design, and in particular, SOI integrated circuit design. Potentially destructive electrostatic pulses, which are known as ESD events, are typically caused by various transient sources such as human or machine handling of the integrated circuit chip during processing, assembly and installation. Most ESD events originate at one of the integrated circuit pads. Since output buffers are typically connected to an integrated circuit pad, it is desirable to provide some sort of ESD protection to the output buffer circuitry.
A typical ESD event includes a high voltage pulse to the output pad, resulting in a high discharge current path through one of the PMOS or NMOS transistors of the output buffer to Vdd or Vss, respectively. For the NMOS transistor, and depending upon the polarity of the ESD voltage pulse supplied to the pad, the discharge path may proceed either via an avalanche breakdown of the drain/body junction or via the forward biasing of the drain/body diode. The avalanche breakdown type of discharge path is the most destructive since it is most likely to result in irreversible damage to the structure of the NMOS transistor. A similar discharge path may exist through the PMOS transistor.
Several approaches for providing ESD protection to SOI CMOS integrated circuits are discussed in “CMOS-On-SOI ESD Protection Networks”, Voldman et al., EOS/ESD Symposium
96-291
, page 6.5.1, and “Dynamic Threshold Body- and Gate-Coupled SOI ESD Protection Networks”, Voldman et al., EOS/ESD Symposium
97-211
, page 3A.2.2. A limitation of many of these prior art approaches is that one or more dedicated devices must be provided to implement the ESD protection function. These dedicated ESD devices are often relatively large, and thus consume a substantial amount of area. Further, the dedicated ESD devices are typically pre-fabricated in and around the perimeter of the device near the I/O pads, and thus are not part of the sea-of-transistors or sea-of-gates region of the integrated circuit. Instead, and as indicated above, they are typically fabricated into the under-layers of the outer perimeter of the integrated circuit, regardless of whether they are actually used in a particular Application Specific Integrated Circuit (ASIC) personality or configuration.
What would be desirable, therefore, is an output buffer with built-in ESD protection, wherein the ESD protection is provided at least in part by selected transistors in the sea-of-transistors or sea-of-gates region of the integrated circuit. This may eliminate the need for at least some of the dedicated “ESD” devices, and in particular, those dedicated ESD devices that are pre-fabricated into the under-layers in and around the perimeter of the integrated circuit. An advantage of such an approach is that only those transistors that are actually needed to provide the desired ESD protection for the particular ASIC personality or configuration are used, thereby maximizing the overall density of the integrated circuit.
SUMMARY OF THE INVENTION
The present invention overcomes many of the disadvantages of the prior art by providing an output buffer with built-in ESD protection, wherein the ESD protection is implemented at least in part from selected transistors in the sea-of-transistors or sea-of-gates region of the integrated circuit. This may eliminate the need for dedicated “ESD” devices, and in particular, those dedicated ESD devices that are pre-fabricated into the under-layers in and around the perimeter of the integrated circuit.
In a first illustrative embodiment of the present invention, a high performance CMOS buffer is provided with a first p-channel transistor and a first n-channel transistor connected in series between a power supply voltage and ground. The gate of the first p-channel transistor and the gate of the first n-channel transistor are coupled to the input terminal of the CMOS buffer. To increase the speed and to ensure that the body of the first p-channel transistor does not float, a first coupler circuit is provided. The first coupler circuit couples the body of the first p-channel transistor to the output terminal of the CMOS buffer when the gate of the first p-channel transistor is low, and couples the body of the first p-channel transistor to the power supply terminal of the CMOS buffer when the gate of the first p-channel transistor is high.
Likewise, to increase the speed and to ensure that the body of the first n-channel transistor does not float, a second coupler circuit is provided. The second coupler circuit couples the body of the first n-channel transistor to the output terminal of the CMOS buffer when the gate of the first n-channel transistor is high, and couples the body of the first n-channel transistor to the ground terminal of the CMOS buffer when the gate of the first n-channel transistor is low.
Preferably, the first coupler circuit includes a second p-channel transistor and a second n-channel transistor. The source and body of the second p-channel transistor is preferably coupled to the power supply terminal of the CMOS buffer. The drain of the second p-channel transistor is preferably coupled to the body of the first p-channel transistor. Finally, the gate of the second p-channel transistor is preferably coupled to the input terminal of the CMOS buffer. The source of the second n-channel transistor is preferably coupled to the body of the first p-channel transistor. The body and drain of the second n-channel transistor are preferably coupled to the output terminal of the CMOS buffer. Likewise, the gate of the second n-ch

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