High performance multiplexer for improving bit error rate

Details High performance multiplexer for improving bit error rate High performance multiplexer for improving bit error rate

1991-08-22

1993-01-26

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307529, 328104, 370112, H03K 1756, H03K 1700

Patent

active

051824671

ABSTRACT:
An apparatus and method for improving the bit error rate of multiplexed signals in a multiplexer system includes independently controlling two types of timing errors. The first type of timing error is related to the timing of transitions between alternating portions of the multiplexed output signal. The second type of timing error is related to the amplitude of the crossing points of the multiplexed signal portions. Varying the duty cycle of the clock signal to the multiplexer controls the transition between the alternating portions of the multiplexed output signal, and adding a voltage offset between single-ended components of the multiplexed output signal controls the amplitude of the crossing points between the one/zero and zero/one transitions of the multiplexed outut signal. The two types of timing errors are controlled with two separate control voltage ports that are independently and continuously variable in order to achieve the optimum bit error rate.

REFERENCES:
patent: 3721959 (1973-03-01), George
patent: 4835771 (1989-05-01), Moussie
patent: 4939729 (1990-07-01), Weisser
patent: 4970410 (1990-11-01), Matsushita

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