High performance multifunction direct memory access (DMA) contro

Details High performance multifunction direct memory access (DMA) contro High performance multifunction direct memory access (DMA) contro

1997-02-10

1998-10-20

Shin, Christopher B.

395555, 395559, G06F 900

Patent

active

058261060

ABSTRACT:
A direct memory access (DMA) controller having memory to memory data transfer capability, a programmable fixed priority scheme, a programmable wait state, a buffer chaining mode data transfer capability, a cascade-master mode, separate channels for internal and external devices, and a programmable 8 or 16 bit requester bus size. The DMA controller includes a channel circuit connected to transfer data to and from a port, a CPU interface, a bus connected to the channel circuit and to the CPU interface to transfer data therebetween, a state machine which generates a clock signal that is used for transferring data from the channel circuit across the bus to the CPU interface, the state machine having a programmable wait state which delays the transfer of data for a preprogrammed number of clock cycles, and a data mode register which is used for setting the preprogrammed number of clock cycles.

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