High-performance multi-processor having floating point unit

Details High-performance multi-processor having floating point unit High-performance multi-processor having floating point unit

1995-04-03

1998-09-15

Eng, David Y.

Boots, shoes, and leggings

3649371, 364258, G06F 9302

Patent

active

058093206

ABSTRACT:
A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queuing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A floating point processor function is integrated on-chip, with enhanced speed due to a bypass technique; a trial mini-rounding is done on low-order bits of the result, and if correct, the last stage of the floating point processor can be bypassed, saving one cycle of latency.

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Intel product book, "387.TM. DX Math Coprocessor", Oct. 1989, pp. 4-305 to 4-340.
Intel product book, "i486.TM. Microprocessor", Nov. 1989, pp. 4-1, 4-10, 4-11, 4-34, 4-35, 4-142 to 4-155.

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