High performance multi-chip flip chip package

Details High performance multi-chip flip chip package High performance multi-chip flip chip package

2011-02-22

2011-02-22

Luu, Chuong A. (Department: 2892)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S108000, C438S127000, C438S114000

Reexamination Certificate

active

07892884

ABSTRACT:
A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

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