High-performance memory interface circuit architecture

Details High-performance memory interface circuit architecture High-performance memory interface circuit architecture

2011-06-28

2011-06-28

Luu, An T (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000, C327S159000

Reexamination Certificate

active

07969215

ABSTRACT:
A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

REFERENCES:
patent: 6100735 (2000-08-01), Lu
patent: 6956418 (2005-10-01), Kwak et al.
patent: 7737741 (2010-06-01), Ma

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