High-performance memory controller with application-programmable

Details High-performance memory controller with application-programmable High-performance memory controller with application-programmable

1991-09-27

1993-10-12

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

365203, G11C 700, G11C 800

Patent

active

052532143

ABSTRACT:
A memory controller (18) for controlling a multiplexed-address memory (14) includes a programmable timer (22) whose time-out period can be controlled by the memory-access device (12) to which the memory controller (18) provides memory access. During an idle period after a memory access, the controller's memory operator (20) keeps the row-address-strobe signal asserted, and thereby permits page-mode addressing on the next cycle, until the counter (22) times out, at which point the memory operator (20) releases the row- address-strobe line and thereby initiates the pre-charge operation that is required before a row-address change. The memory access device (12) can thus change the time for which the row-address-strobe signal is kept asserted after a cycle to different values for different applications that it is running. The memory-access device (12) can thus optimize, on an application-specific basis, the compromise between the pre-charge penalties of page misses and the column-address-only benefits of page hits.

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