High performance, low power, scannable flip-flop

Details High performance, low power, scannable flip-flop High performance, low power, scannable flip-flop

2000-05-05

2002-02-19

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S202000, C327S203000

Reexamination Certificate

active

06348825

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to flip-flop circuits, and, in particular, to a scannable, dual-edge pulse-triggered flip-flop.
2. Background Art
In general, in the descriptions that follow, we will italicize the first occurrence of each special term of art which should be familiar to those skilled in the art of designing integrated circuits. In addition, when we first introduce a term that we believe to be new or that we will use in a context that we believe to be new, we will bold the term and provide the definition that we intend to apply to that term. In addition, throughout this description, we may use the terms assert and negate when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively. For convenience, we will indicate an active low signal by appending an asterisk (“*”) to the signal name.
Scan testing is a common and widely used technology to achieve verifiable high fault coverage in digital designs. The two most commonly used scan techniques are muxed scan and Level Sensitive Scan Design or LSSD. Scan cells are usually implemented with minimum size transistors to have the least impact on area and speed. Since scan is a test mode, it is generally relegated to running at low speeds because its primary use is in detecting stuck-at faults.
Design geometries continually shrink to achieve higher performance and density. Scan design typically follows functional design and many configurations are available for the design of flip-flops. In a typical single edge-triggered flip-flop design, data is captured on only a single edge of the clock. In a dual edge-triggered design, two single edge-triggered flip-flops are coupled in parallel so that each captures data on respective edges of the clock. Thus, the clock frequency can be reduced in half with the same data rate, thereby saving very significant power in the clock tree network. Since in high performance designs, as much as half of the power of the chip can be consumed by the clock network, using dual edge-triggered designs can reduce overall chip power by up to a quarter. Dual edge-triggered flip-flops are, however, difficult to make low power. Furthermore, using both edges of the clock is inherently a testability problem since one of the primary rules for scan design is to capture data on only one edge of the clock.
As clock periods decrease in high performance designs, the clock cycle time becomes a critical design factor. Latch-based designs allow for time borrowing between stages of logic. This often can balance the delay between two stages of logic to allow a higher performance target to be achieved. However, in typical flip-flop based designs, no time borrowing between stages of logic is possible. Pulse-triggered flip-flops can be used to solve this problem, because they allow for some time borrowing to achieve maximum performance, yet remain a flip-flop based design. Since pulse-triggered flip-flops need only a single data latch instead of the pair of back-to-back data latches used in typical flip-flop designs, the propagation delay of the flip-flop is also significantly reduced. One technique to generate the clock pulses from a single clock is to use a two-input AND gate with one input coupled directly to the clock and another input coupled to the clock via an inverter chain. Data is clocked into the flip-flop for the short duration of each pulse. The number of inverter stages determines the pulse width, which in turn determines how much time borrowing is allowed. A trade-off must be made between making the pulse wider, which allows for more time borrowing, or narrower, which reduces the hold time requirement of the flip-flop.
If the circuit speed is adequate, a pulse-triggered circuit can be triggered on both edges of the clock. To generate the required double-rate clock pulses, an Exclusive Or gate may be substituted for the AND gate. However, there is no known dual-edge pulse-triggered flip-flop that is scannable.
What is needed, therefore, is a high performance, low power, scannable flip-flop.
BRIEF SUMMARY OF THE INVENTION
In accordance with our invention, we have provided a dual-edge pulse-triggered flip-flop that is a combination of design techniques for high performance, low power, and scan testability.


REFERENCES:
patent: 4495628 (1985-01-01), Zasio
patent: 5003204 (1991-03-01), Cushing et al.
patent: 5619157 (1997-04-01), Kumata et al.
patent: 5689517 (1997-11-01), Ruparel

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