High performance, low power incrementer for dynamic circuits

Details High performance, low power incrementer for dynamic circuits High performance, low power incrementer for dynamic circuits

1996-01-04

2001-08-21

Mai, Tan V. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06279024

ABSTRACT:

FIELD OF THE INVENTION
The invention is a dynamic incrementer, implemented in the Self Resetting Complementary Metal Oxide Semiconductor (SRCMOS) circuit family, which internally performs single rail calculations and which generates the dual rail result using a strobing technique. The carry-lookahead function is implemented with an OR tree using the complement input signals, resulting in a very fast and economical incrementer.
BACKGROUND OF THE INVENTION
Circuits which perform addition by 1, known as incrementers, are widely used in microprocessors due to the sequential nature of instruction generation and execution. Implementation in dynamic logic offers considerable speed advantages. However, adders and incrementers use both true and complement signals. In dynamic logic schemes, if both true and complement (“dual rail”) signals are required, they usually have to be generated in parallel from the preceding latch, thereby consuming twice the area of and dissipating more power than single-rail logic. Therefore an optimized incrementer can provide a reduction in area and in power dissipated across an entire microprocessor chip.
In an incrementer, as in an adder, the critical path consists of the calculation of the carry signals. These are usually calculated by the use of an AND tree, which can be 64 high in state of the art 64-bit microprocessors. This limits the achievable speed.
SUMMARY OF THE INVENTION
The invention is comprised of an incrementer architecture based on a single rail, negative logic OR tree for the carry look-ahead function. Such an OR function is faster, dissipates less power, and occupies considerably less area than a corresponding AND function.
The dual rail sum is calculated using a strobed XOR function. This strobing technique eliminates the duplication associated with calculating both true and complement signals from the start.
This incrementer can be constructed using all types of dynamic logic whether the reset signal is generated locally, as in Self Resetting CMOS (SRCMOS) logic, or clock distributed as e.g., in Domino logic (see Weste and Eshragian, “Principles of CMOS VLSI Design: A systems perspective”, Addison Wesley, Reading Mass., 1988).
The above architecture allows this incrementer to be used in high speed circuits with low latency and fast cycle time.


REFERENCES:
patent: 3989940 (1976-11-01), Kihara
patent: 4417315 (1983-11-01), Russell
patent: 5345110 (1994-09-01), Renfro et al.
patent: 5384724 (1995-01-01), Jagini
“FET DRAM Look-Ahead Address Incrementer” IBM, Tech. Discl. Bul., vol. 28 No. 1 Jun. 1985, pp. 71-73.

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