High performance, low-leakage static random access memory...

Details High performance, low-leakage static random access memory... High performance, low-leakage static random access memory...

2005-05-11

2009-02-10

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S226000

Reexamination Certificate

active

07489584

ABSTRACT:
Systems and methods are provided for reducing leakage current and maintaining high performance in a static random access memory (SRAM). One embodiment discloses a memory array system operative to store data bits in individually addressable rows and columns. The memory array system comprises a plurality of memory blocks, each of the plurality of memory blocks having a plurality of memory rows and a row peripheral circuit operative to switch a memory block from a retention mode to an activation mode in response to an addressing of a memory row within the memory block.

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