High performance Lempel Ziv compression architecture

Details High performance Lempel Ziv compression architecture High performance Lempel Ziv compression architecture

2006-09-19

2006-09-19

Barnie, Rexford (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Adaptive coding

C341S063000, C341S065000, C341S067000, C341S106000

Reexamination Certificate

active

07109895

ABSTRACT:
A data compression architecture includes a shift register with multiple shift register elements. A data input receives input data characters, and applies each received input data character to the shift register, such that the received input data character is stored in each shift register element of said shift register in turn. Logic circuitry is associated with each shift register element of the shift register, for detecting a match when the comparison circuitry determines that a sequence of two or more received input data characters is equal to a sequence stored in the shift register. A flush input receives a data flush input signal, and applies a received data flush input signal to the logic circuitry associated with each shift register element of the shift register, such that no match is detected by said logic circuitry when the data flush input signal is received.

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