High performance latch circuit

Details High performance latch circuit High performance latch circuit

1975-06-30

1976-10-12

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307208, 307213, 307215, 307217, 307299A, 307317A, H03K 3286, H03K 1908, H03K 1934, H03K 1938

Patent

active

039860574

ABSTRACT:
Disclosed is a high performance logically hazard-free latch circuit compatible with TTL technology. The occurrence of both a clock and data signal provides an inverted data output signal at the output node which is fed back to the base electrode of a multi-emitter transistor. The output node then remains latched at the desired logic level until the occurrence of a subsequent clock signal. Also disclosed are techniques for improving the capabilities of the latch and for accepting additional clock and data inputs. The polarity-hold latch circuit disclosed herein is advantageously implemented in semiconductor integrated circuit technology.

REFERENCES:
patent: 3283170 (1966-11-01), Buie
patent: 3783254 (1974-01-01), Eichelberger
solid State Products, Inc., Bulletin, D420-02-12-59, Dec. 1959, pp. 22-24.
Bodendorf et al., "Hazard-Free and Nonsaturating Polarity-Latch," IBM Tech. Discl. Bull., vol. 14, No. 7, p. 2046, Dec. 1971.
Palmieri, "DC Trigger Circuit," IBM Tech. Discl. Bull., vol. 13, No. 5, p. 1075, Oct. 1970.

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