High performance IP processor

Electrical computers and digital processing systems: multicomput – Network-to-computer interfacing

Reexamination Certificate

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Reexamination Certificate

active

07487264

ABSTRACT:
An architecture provides capabilities to transport and process Internet Protocol (IP) packets from Layer2through transport protocol Layer and may also provide packet inspection through Layer7. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory.

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