High performance intermediate stage circuit for a...

Details High performance intermediate stage circuit for a... High performance intermediate stage circuit for a...

2001-09-10

2002-05-07

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S255000, C330S288000

Reexamination Certificate

active

06384683

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high performance intermediate stage for an operational amplifier (opamp), where the opamp accepts a rail-to-rail input voltage and provides a rail-to-rail output voltage. More particularly, the present invention relates to an intermediate stage with a floating current source used to bias two current mirrors, where the floating current source has circuitry configured to minimize input offset voltage and to provide currents which do not vary with changes in the voltage rails or the common-mode input voltage.
2. Background
FIG. 1
shows typical circuitry for an opamp which accepts a rail-to-rail input voltage, or voltage ranging between the V
DD
and V
SS
voltage supply rails, and provides a rail-to-rail output voltage. The circuit includes an input stage
100
, an intermediate stage
150
, and an output stage
190
.
The input stage
100
is formed by transistors
101
-
104
, a current source
106
and a current source
108
. The gates of transistors
101
and
102
provide the inverting input V
IN
− for the opamp, while the gates of transistors
103
and
104
provide the noninverting input V
IN
+. The current source
106
drives the sources of transistors
101
and
104
, while the drains of transistors
101
and
104
provide current signals I
IP
+ and I
IP
− to the intermediate stage
150
. The current source
108
provides current to the sources of transistors
102
and
103
, while the drains of transistors
102
and
103
provide current signals I
IN
− and I
IN
+ to the intermediate stage. Transistors
101
and
104
are PMOS transistors as illustrated by the circle provided on their gate, while transistors
102
and
103
are NMOS devices without such a gate circle. The gate circles are used to show which transistors are PMOS and NMOS devices in the remaining transistors of
FIG. 1
, as well as in transistors in subsequent figures.
The intermediate stage
150
includes two current mirrors, a first current mirror with transistors
151
-
154
, and a second current mirror with transistors
155
-
158
. The intermediate stage also includes voltage supplies
160
and
162
. The voltage supply
160
biases the gates of transistors
153
and
154
, while the voltage supply
162
biases the gates of transistors
155
and
156
.
The intermediate stage further includes a current source
164
set to provide a current to bias the gates of current mirror transistors
151
and
152
and to drive the drain of transistor
153
. A current source
166
biases the gates of current mirror transistors
157
and
158
and provides current from the drain of transistor
155
.
Outputs I
OP
and I
ON
of the intermediate stage are provided from the source and drain of transistors
170
and
180
with source-drain paths connected in parallel between the drains of transistors
154
and
156
. Transistors
171
and
172
are diode connected transistors which set the bias voltage on the gate of transistor
170
. A current source
173
drives the gate of transistor
170
as well as transistors
171
and
172
. Transistors
181
and
182
are diode connected transistors which set the bias voltage on the gate of transistor
180
. A current source
183
provides current to transistors
181
and
182
to bias the gate of transistor
180
.
The output stage
190
includes output driver transistors
192
and
194
connected between the rails V
DD
and V
SS
. The common drains of transistors
192
and
194
provide the output of the CMOS opamp of FIG.
1
. The gate of transistor
192
is driven by the output I
OP
of the intermediate stage. The gate of transistor
194
is driven by the output I
ON
of the intermediate stage. A capacitor
196
is connected between the gate of transistor
192
and its drain to provide Miller Effect frequency compensation. Similarly, a capacitor
198
is provided between the gate and drain of transistor
194
.
The intermediate stage provides a stable class A-B control for the output stage independent of common-mode input and supply rail voltages. A drawback to the circuit is that any mismatch between the current sources
164
and
166
will reflect forward as an input offset. The circuit of
FIG. 1
is described in Hogervorst, et al., “A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input/Output Operational Amplifier For VLSI Cell Libraries”,
IEEE Journal Of Solid-State Circuits
, Vol. 29, No. 12, December 1994, which is incorporated herein by reference (‘the Hogervorst reference’).
FIG. 2
shows modifications to the intermediate stage circuit
150
of
FIG. 1
to overcome the problem of input offset being reflected forward due to a mismatch between current sources
164
and
166
. The intermediate stage circuit of
FIG. 2
includes an ideal floating current source
200
which is used instead of current sources
164
and
166
. The ideal floating current source
200
connects the gates of current mirror transistors
157
-
158
and drain of transistor
155
to the gates of current mirror transistors
151
-
152
and drain of transistor
153
. The constant values of the floating current source
200
together with the current sources
171
and
173
control the output stage's quiescent current to be constant. Note that components carried over from
FIG. 1
to
FIG. 2
are similarly labeled, as are components carried over in subsequent figures.
FIG. 3
shows one implementation of circuitry to provide the ideal floating current source
200
of FIG.
2
. The ideal floating current source includes two transistors
304
and
312
with source to drain paths connected in parallel between the drains of transistors
153
and
155
. The gate of transistor
304
has a voltage set by diode connected transistors
300
and
302
and is driven by current source
306
to the V
DD
voltage rail. The gate of transistor
312
has a voltage set by diode connected transistors
308
and
310
and is connected by a current source
314
to the V
SS
voltage rail. As configured, the transistors
304
and
312
provide two identical current sources between current mirrors formed by transistors
151
-
154
and transistors
155
-
158
, so that the current source transistors
304
and
312
do not reflect forward an input offset voltage, unlike the current sources
164
and
166
of
FIG. 1
which may be mismatched.
The bias currents of transistors
304
and
312
will change when the common mode input cuts off one of the currents I
IN
−/I
IN
+ and I
IP
+/I
IP
−. If the input common mode value goes to V
SS
, then I
IN
+/I
IN
− will collapse to zero current. If that happens, the current mirror
155
-
158
will change DC operating voltage, and the PMOS transistor
312
will change its gate to source voltage, and therefore assume a new bias current to change the A-B point for the output stage. Similarly, if the input common mode value goes to V
DD
, I
IP
+/I
IP
− will collapse to zero current, the current mirror
151
-
154
will change operating voltage, and the NMOS transistor
304
will change its gate-to-source voltage. The NMOS transistor
304
will, therefore, assume a new bias current to change the A-B point for the output stage. The transistors
312
and
304
are, thus, sensitive to input common mode changes. The current of the floating current source will, thus, change with the common-mode input voltage, and therefore the quiescent current of the output stage will also change to compensate for the common mode input voltage. The circuitry of
FIG. 3
is described in the Hogervorst reference cited previously.
FIG. 4
shows another circuit implementation for the ideal floating current source
200
of FIG.
2
. The current source includes two transistors
402
and
404
with source to drain paths connected in series between the drains of transistors
153
and
155
. The gate of transistor
402
is driven by a current source
405
and is further connected to one leg of a current mirror formed by transistors
406
and
407
. The other leg of

Affiliated with

Also associated with

Rating

High performance intermediate stage circuit for a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High performance intermediate stage circuit for a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance intermediate stage circuit for a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2823100