High performance interface logic architecture of an...

Details High performance interface logic architecture of an... High performance interface logic architecture of an...

2007-10-23

2007-10-23

Sam, Phirin (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S389000, C370S420000

Reexamination Certificate

active

09791063

ABSTRACT:
An aggregation router architecture comprises a plurality of line cards coupled to at least one performance routing engine (PRE) via an interconnect system. The line cards include input cards having input ports coupled to subscribers and at least one trunk card configured to aggregate packets received from the subscriber inputs over at least one output port. The PRE performs packet forwarding and routing operations, along with quality of service functions for the packets received from each input line card over the interconnect system. The interconnect system comprises a plurality of high-speed unidirectional (i.e., point-to-point) links coupling the PRE to each line card. The point-to-point links couple the line cards to a novel logic circuit of the PRE that is configured to interface the line cards to a packet buffer and a forwarding engine of the PRE.

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