High performance instruction data path

Details High performance instruction data path High performance instruction data path

1995-11-17

1998-03-03

Treat, William M.

395591, G06F 9312

Patent

active

057245339

ABSTRACT:
A method of and apparatus for efficiently halting the operation of the instruction processor when a cache miss is detected. Generally, this is accomplished by preventing unwanted address incrementation of an instruction address pipeline and by providing a null instruction to an instruction pipeline when a cache miss is detected. Accordingly, the present invention may eliminate a recovery period after a cache miss, thereby enhance the performance of the data processing system. Further, the present invention may eliminate recovery hardware required to support the recovery process.

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