Multiplex communications – Wide area network – Packet switching
Patent
1991-07-22
1994-01-04
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
395275, 395325, 370 851, H04J 324
Patent
active
052766845
ABSTRACT:
An I/O Processor (28) includes a two channel receiver (28b) and a two channel transmitter (28c) coupled to a high speed communications channel. For the receiver a status memory, specifically a FIFO (44a, 44b), stores structuring information that indicates the beginnings (SOP) and endings (EOP) of PACKETS, as well as, for each BURST of data words within a packet, an indication of the occurrence of the BURST and a length (L) of the BURST. Additionally, there is an indication for each BURST of the presence of any errors occurring during the BURST. A corresponding data FIFO (40a, 40b) contains only the received data words, without any structuring information. A device reads both of the FIFOS, subsequent to the reception of one or more PACKETS, so as to reconstruct the original format of the received data. For the transmitter a structure control FIFO (46a, 46b) stores the structuring information for an associated data FIFO (40c, 40d) , the transmitted data being structured in accordance with the structuring information. The receiver and the transmitter each include a high speed internal data path (42a, 42b) and a lower speed data path (54a, 54b) which are coupled together during slave read and write cycles, and which are decoupled during high speed DMA cycles.
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Supercomputers: Technology and Applications; G. J. M. Smit, P. G. Jansen; Microprocessing and Microprogramming vol. 24, 1-5; Zurich, Aug. 29-Sep. 1, 1988.
International Business Machines - Corporation
Olms Douglas W.
Ton Dang
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