High performance, high bandwidth memory bus architecture utilizi

Details High performance, high bandwidth memory bus architecture utilizi High performance, high bandwidth memory bus architecture utilizi

1997-05-21

1999-02-09

Hoang, Huan

Static information storage and retrieval

Addressing

Sync/clocking

36523002, 36523003, 36518902, 365221, G11C 800

Patent

active

058703500

ABSTRACT:
A high performance, high bandwidth memory bus architecture and module. The module may be a card that includes standard synchronous DRAM (SDRAM) chips and reduces latency and pin count. Four bus pins separate input commands from data and establish parallel system operations. By maintaining "packet" type transactions, independent memory operations can be enhanced from that of normal SDRAM operations. The architecture divides its buses into command and data inputs that are separate from output data.

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