Fishing – trapping – and vermin destroying
Patent
1995-01-19
1995-12-26
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437 45, 437157, H01L 21266
Patent
active
054787637
ABSTRACT:
A method is provided for fabricating a MOSFET transistor device with a gate formed over a lightly doped semiconductor substrate with a gate, and a source region and a drain region. V.sub.T1 ions are uniformly implanted into the surface of the substrate forming a V.sub.T region with substantially uniform doping in the upper portion of the substrate near the surface thereof. A gate oxide layer is formed on the substrate. A gate conductor is deposited over the gate oxide layer. A large angle implant is implanted into the region of the device over the source region. Then ions are implanted to form the source and drain regions which are self-aligned with the gate.
REFERENCES:
patent: 5079620 (1992-01-01), Shur
patent: 5292674 (1994-03-01), Okabe et al.
patent: 5355006 (1994-10-01), Iguchi
Chaudhari Chandra
Jones II Graham S.
Saile George O.
United Microelectronics Corporation
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