High performance, fault tolerant orthogonal shuffle memory and m

Details High performance, fault tolerant orthogonal shuffle memory and m High performance, fault tolerant orthogonal shuffle memory and m

1991-04-08

1997-03-18

Baker, Stephen M.

Excavating

365 75, 365 77, 365 78, 371 402, G11C 1900, G11C 2100, G11C 2900

Patent

active

056129645

ABSTRACT:
A high performance fault tolerant orthogonal shuffle memory comprising a plurality of memory cells arranged to form a two-dimensional array of rows and columns. Each memory cell includes a data store element for storing data and a multi-state data transmission element to provide access to the data stored in the data store element. Each memory cell has the dual function of storing and transmitting (i.e. shifting) data. The memory cell array is coupled to first and second registers and a shuffle signal generator. In operation, data is shuffled column by column through the array, such that only two columns of memory cells are activated at any time. The shuffle memory herein disclosed may form subarrays of each of a data storage array and a redundancy storage array that are coupled to an improved error detector and corrector to form a high performance fault tolerant orthogonal memory system.

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"Novel Fault-Tolerant Circuits For Configurable Mass Memories", T.P. Haraszti et al, Proceedings of The IEEE Custom Integrated Circuits Conference, May 13-16, 1990, pp. 19.5.1-19.5.4.

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