High performance equalizer having reduced complexity

Details High performance equalizer having reduced complexity High performance equalizer having reduced complexity

2006-03-14

2006-03-14

Phu, Phuong (Department: 2631)

Pulse or digital communications

Equalizers

Automatic

C375S232000, C708S322000, C708S323000

Reexamination Certificate

active

07012957

ABSTRACT:
An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.

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