High performance dynamic sense amplifier with active loads

Details High performance dynamic sense amplifier with active loads High performance dynamic sense amplifier with active loads

1978-09-22

1980-12-16

Anagnos, Larry N.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307279, 307DIG3, 365205, H03K 524, H03K 3356, G11C 700

Patent

active

042399939

ABSTRACT:
A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.

REFERENCES:
patent: 3909631 (1975-09-01), Kitigawa
patent: 3949381 (1976-04-01), Dennard et al.
patent: 4000413 (1976-12-01), Wong et al.
patent: 4003034 (1977-01-01), Au
patent: 4050061 (1977-09-01), Kitigawa
patent: 4061999 (1977-12-01), Proebsting et al.
patent: 4070590 (1978-01-01), Ieda et al.
patent: 4081701 (1978-03-01), White, Jr. et al.
patent: 4125878 (1978-11-01), Watanabe
patent: 4144590 (1979-03-01), Kitigawa et al.
patent: 4150311 (1979-04-01), Matsuda et al.
Cassidy et al., IBM Technical Bulletin, vol. 20, No. 1, pp. 268-269, 6/1977.
Bishop et al., IBM Technical Disclosure Bulletin, vol. 18, No. 4, pp. 1021-1022, 9/1975.
Electronics (pub.) (by Kuo et al.), pp. 81-86, 5/13/76.

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