High performance dynamic sense amplifier voltage boost for row a

Details High performance dynamic sense amplifier voltage boost for row a High performance dynamic sense amplifier voltage boost for row a

1980-10-22

1985-09-24

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307578, 365205, 365230, H03K 524, G11C 706, G11C 800

Patent

active

045435006

ABSTRACT:
A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled drive transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.

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Kuo et al., "16-K RAM Built with Proven Process May Offer High Start-Up Reliability"; Electronics (pub.) pp. 81-86; 5/13/76.
Gray, "Three Level Word Line Pulse for Single FET Cell Arrays"; IBM Tech. Discl. Bull.; vol. 20, No. 5, pp. 1718-1719; 10/1977.
Rossi, "Bilevel Word Driver for Single-Device Cells"; IBM Tech. Discl. Bull.; vol. 18, No. 7, pp. 2089-2090; 12/1975.

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