High performance digital phase locked loop

Details High performance digital phase locked loop High performance digital phase locked loop

1992-06-15

1994-10-11

Callahan, Timothy P.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307511, 307262, 328133, 328155, 377 76, H03K 1728

Patent

active

053550374

ABSTRACT:
A first periodic digital waveform is to be synchronized with a second periodic digital waveform obtained by propagating the first waveform through a delay path (13) having an adjustable propagation delay. In the disclosed approach, the delay of the delay path is increased, even when an edge (43) of the second waveform trails a corresponding edge (45) of the first waveform by less than one-half cycle. The delay continues to be increased until the edge of the second waveform is eventually time-shifted past the next successive corresponding edge (49) of the first waveform.

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patent: 4656369 (1987-04-01), Lou
patent: 4751469 (1988-06-01), Nakagawa et al.
patent: 4795964 (1989-01-01), Mahant-Shetti et al.
patent: 5227675 (1993-07-01), Taguchi
"A Fully Digital Phase Locked Loop", Victor Menasce et al., Canadian Conference on Very Large Scale Integration, Oct. 1990, pp. 9.4/1-9.4/8.
"ASIC Clock Distribution Using A Phase Locked Loop (PLL)", Laurin Ashby, Conference Proceedings from 1991 IEEE ASIC Seminar and Exhibit, 1991, pp. P1-6.1-P1-6.3.

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