High performance debug I/O

Details High performance debug I/O High performance debug I/O

1999-07-12

2000-01-04

Picardat, Kevin M.

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

438 4, 438 12, 438 14, H01L 2166

Patent

active

060109157

ABSTRACT:
A semiconductor with dedicated wire bond sites that are routed and via'd only to a top surface of a semiconductor package to flush mount pads where they are probed during debug, thus reducing the overall inductance and capacitance of the path from the wire bond site to the debug probing site over conventional debug testing by means of dedicated pins on the semiconductor package. This design permits higher performance debug data capture, while at the same time decreasing the number of pads and pins that are necessary for debug.

REFERENCES:
patent: 5041899 (1991-08-01), Oku et al.
patent: 5306948 (1994-04-01), Vamada et al.
patent: 5767544 (1998-06-01), Kuroda et al.

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