Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-05-07
2004-05-04
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S518000
Reexamination Certificate
active
06732126
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to datapath circuits in computing systems.
2. State of the Art
Computing systems typically include a datapath for operating on data within the system. In general, the datapath of a computing system includes functional blocks (implemented in either software or hardware) each dedicated to performing a single function.
FIG. 1
shows an example of a simplified datapath system having a typical set of functional blocks including an adder block, an incrementor block, logic function blocks (each performing a different logic function), a barrel shifter block. A common bus having a fixed width couples a dataword to the inputs of the functional blocks wherein only one of the outputs of functional blocks is multiplexed to the output of the datapath.
One problem with this design is that the datapath system is exclusively dedicated to the current operation it is performing such that only a single dataword can be operated on by a single functional block at one time thereby causing a bottleneck at the input of the datapath. In the field of communications in which high frequency real-time data is processed, a bottleneck at the input of the datapath represents a significant reduction in overall system performance. Alternatively, more functional blocks can be added, however, this represents an increase in design size.
In addition, since the common input bus is a fixed width, if a dataword having a width that is smaller than the common bus width is processed by the datapath only a portion of the common bus width is used and the remainder is wasted resulting in an inefficient utilization of bandwidth. Finally, in prior art systems the bus width into the datapath becomes the limit of your data throughput. For instance, if you have a 32-bit bus width into the datapath and it is desired to transfer 64-bits, it would be necessary to perform this in two transfer operations.
The present invention is a system and method of designing a configurable datapath which allows for a variable width datapath and which is programmable so as to perform a variety of data functions using the same datapath unit.
SUMMARY OF THE INVENTION
A programmable and configurable datapath unit (DPU) includes a configuration of N interconnected single-bit multi-function processing units (PUs) configured into at least a row of PUs. The PUs are controlled by the same control signal such that the datapath unit is programmable to perform a selected N-bit function dependent on the control signal. The DPU is configurable in that it can be interconnected with other DPUs to increase its data throughput. In one embodiment each PU is implemented as a modified adder, each having at least first and second single-bit inputs, a carry input, a control signal input, a carry output, and a sum output. In this embodiment, the adders are interconnected such that the carry output of a given PU in the configuration is coupled to the carry input of the adjacent PU in the configuration. Each of the adders are implemented with logic gates such that intermediate logic operation resultants can be obtained from each adder. The intermediate operation resultants are internally multiplexed to the sum output port of the adder along with the addition resultant. The control applied to the control input of each adder selects which resultant is internally multiplexed to the sum output port of each PU. Each PU can also include boolean logic circuitry for performing other logic functions which are multiplexed to its sum output port. In one embodiment, the DPU is controlled to perform any of the following functions including addition, subtraction, multiplexing, incrementing, standard and custom logic functions, and conditional operations. In another embodiment, multiplexers are used to direct input and output data through each PU dependent on the selected function being performed.
The DPU input operand width is dependent on the number of single-bit PUs in a given row. In accordance with a system and method of the present invention, more than one DPU can be interconnected and programmed to form a datapath circuit having a wider input/output bit operand. In one embodiment, each individual DPU has four single-bit PUs in a single row so that it can be combined with other similar DPUs to form 4(n)-bit datapath circuits.
In accordance with another system and method of the present invention, more than one DPU is configured into an array. Groups of DPUs are interconnected and programmed to form multiple datapath circuits. The datapath circuits, in turn, are interconnected to form a datapath system made-up of the multiple datapath circuits each capable of performing a different function and having a different input and output operand widths. In one embodiment, the array comprises eight DPUs in each row and the array includes 32 rows.
In another embodiment, the DPU is designed so that it can be configured to perform a multiplication function in addition to standard and customized logic functions, conditional functions, and arithmetic functions. The DPU includes an array of eight single-bit modified adders, having four adders in a top row and four adders in a bottom row so as to form four pairs of stacked adders. The DPU further includes sets of multiplexers for directing the dataflow through the configuration of adders dependent on the function being performed by the DPU. The DPU is adapted for stacking and interconnecting rows of DPUs to form an array of DPUs which performs a first step of the multiplication operation. Additional adder circuitry performs a second step of the multiplication operation. In one embodiment a portion of a 16×16 bit multiplication circuit is formed by stacking and interconnecting 4 rows of DPUs, each row including 4 DPUs.
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patent: 5805477 (1998-09-01), Perner
Intel Corporation
Malzahn David H.
Proksch Michael A.
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