High performance CPL double-gate latch

Details High performance CPL double-gate latch High performance CPL double-gate latch

2001-02-20

2002-10-08

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S065000, C327S089000, C327S199000, C365S189050, C365S207000

Reexamination Certificate

active

06462585

ABSTRACT:

DESCRIPTION
1. Field of the Invention
The present invention relates to asymmetric-double-gate complementary metal oxide semiconductor (DGCMOS) devices, and more particularly to an asymmetric-DGCMOS device wherein a cross-coupled latch is employed which substantially reduces body-to-source/drain parasitic capacitances as well as structural body resistance parasitics of the asymmetric-DGCMOS device. The inventive DGCMOS device design provides a lower power, higher performance DGCMOS device than heretofore possible with prior art DGCMOS devices.
2. Background of the Invention
Asymmetric-double-gate complementary metal oxide semiconductor (DGCMOS) technology is considered to be the leading candidate to extend high-performance CMOS technology beyond 0.1 &mgr;m lithography and below 1.0 V power supply. Asymmetric-double-gate MOSFET (See, for example, T. Tanaka, et al., “Ultrafast Low-Power Operation of a p+-n+Double-Gate SOI MOSFETS”, 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 11-12) consists of a fully depleted double-gate MOSFET in which the two gate electrodes consist of dissimilar conductors, typically n+and p+doped polysilicon. A typical prior art asymmetric-double-gate device is shown, for example, in
FIGS. 1A and 1B
. Since the two electrodes have differing Fermi levels, one of the two electrodes will prove more attractive to the channel inversion layer, when formed, and thus will exert stronger control of the conduction channel. The electrode which proves more attractive to the inversion carriers is referred to as the “strong”
0
gate and the electrode which proves less attractive is referred to as the “weak”
0
gate.
Conventional CMOS circuits in DGCMOS technology gain from increased effective V
dd
/V
t
ratio due to the ideal sub-threshold swing and improved short-channel V
t
control compared to conventional CMOS. It is noted that the term “V
dd
” is used herein to denote the power supply voltage of the device, whereas the term “V
t
” denotes the threshold voltage of the device. Despite the above-mentioned improvements, the effective V
dd
/V
t
ratio of prior art DGCMOS devices must degrade with V
dd
scaling. Various attempts to further improve the effective V
dd
/V
t
ratio of DGCMOS devices to limits that are within conventional scaling expectations have been developed. One such attempt is disclosed, for example, in Fuse, et al., “0.5V SOI CMOS Pass-Gate Logic”, Slide Supplement for the 1996 IEEE International Solid-State Circuits Conference, Page 71. Specifically, the Fuse, et al. publication discloses a DGCMOS design wherein a variant on dynamic threshold CMOS (DTCMOS) technology is employed. Specifically, the Fuse, et al. publication provides a DTCMOS design where the gates of the nFETs (field effect transistors) are connected to the bodies of the latch pFETs. The input-body connection scheme employed in Fuse, et al. is shown in
FIGS. 2-3
. This prior art scheme includes an inverter with cross-coupled pull-up pMOSFETs.
FIG. 2
illustrates a prior art connection scheme without body-bias controlling, while
FIG. 3
shows a prior art connection scheme with body-bias controlling. In each of
FIGS. 2 and 3
, reference numeral
10
is used to represent pMOSFETs, reference numeral
12
is used to represent an inverter, and reference numerals
14
and
16
are used to denote the point at which cross-coupling between adjacent pMOSFETs occurs.
Dynamic threshold complementary metal oxide semiconductor (DTCMOS) circuits, such as illustrated above and further described in the Fuse, et al. publication, unfortunately suffer from inherent body-to-source and body-to-drain parasitic capacitances as well as structural body resistance parasitics. These parasitics cause an undesirable increase in the gate input capacitance of the device since all the body of the MOSFET serves as a gate electrode. Moreover, in prior art DTCMOS devices, the source and drain regions are only isolated from the switched body by silicon depletion regions that have a high dielectric constant (on the order of about 11.7) associated therewith. A detailed discussion concerning the drawbacks associated with dynamic threshold CMOS circuits can be found, for example, in C. Wann, et al., “Channel Profile Optimization and Device Design for Low-Power High-Performance Dynamic-Threshold MOSFET”, IEDM 96-113.
Due to the above-mentioned disadavantages of the DTCMOS devices, the use of these devices to improve the effective V
dd
/V
t
ratio presents significant shortcomings for power and delay reductions with V
dd
scaling (reduction); therefore alternative solutions for improving effective V
dd
/V
t
ratio without causing any substantial body-to-source or body-to-drain parastic capacitances nor body parastic resistances are needed. Such a solution may lead to extending high-performance CMOS technology beyond 0.1 &mgr;m lithography and below 1.0 V power supply ranges.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a cross-coupled latch circuit which can be used with an asymmetric-double-gate device.
A further object of the present invention to provide a cross-coupled latch circuit that improves the effective V
dd
/V
t
ratio of an asymmetric-double-gate device to a value that is within current scaling expectations.
A yet further object of the present invention is to provide a cross-coupled latch circuit that improves the effective V
dd
/V
t
ratio without causing any substantial body-to-source/drain parasitic capacitances or structural body resistance parasitics.
An even further embodiment of the present invention is to provide a differential circuit design for use with an asymmetric-double-gate complementary metal oxide semiconductor (DGCMOS) device which provides a high performance device that may be scalable below about 0.1 &mgr;m, while being able to operate at voltages below about 1 V.
These and other objects and advantages are achieved in the present invention by providing a differential circuit wherein asymmetric-double-gate CMOS devices are wired with both of the nFET gates tied to the input and one of the pFET (double) gates also tied to the input. The inventive circuit allows the pFET drive to vary on a desirable fashion for speed and stability. Moreover, the inventive differential circuit improves the effective V
dd
/V
t
ratio of the device, without causing any substantial body-to-source/drain parasitic capacitances or structural body resistance parasitics. Additionally, the inventive circuit design provides a high performance asymmetric-DGCMOS device that may be scalable below about 0.1 &mgr;m, yet is able to operate at voltages below about 1 V.
Specifically, the present invention provides a differential circuit which comprises an asymmetric-double-gate device containing a pair of series coupled pFETs and nFETs, each pFET and nFET having weak gates and strong gates associated therewith, wherein the weak gates of the nFETs and the pFETs are tied to input circuitry, and the strong gates of said pFETs are used for cross-coupling.
The inventive circuit design provides a lower power and higher performance device that can be easily integrated into present DGCMOS technology.


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Fuse, T., et al., “0.5V SOI CMOS Pass-Gate Logic”, IEEE International Solid-State Circuits Conference, pp. 88-89, 1996.
Wann, C., et al., “Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET”, IEEE/IEE Electronic Library, Electron Devices Meeting, 1996, International, pp. 113-116, Dec. 1996.
Wann, C., et al., “Channel Profile Optimization and Device Design for Low-Power High-Performance Dynamic-Threshold MOSFET”, IBM T.J. Watson Research Center, Yorktown Heights, New York 10598, 1996.
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