Patent
1988-06-01
1992-04-07
Jackson, Jr., Jerome
357 231, 357 55, 357 71, H01L 2978
Patent
active
051032767
ABSTRACT:
A dRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD. The word line is formed closely adjacent the pillars in its associated row, separated therefrom by a gate dielectric film; the word line is separated from the adjacent row by a dielectric film which is thicker than the gate dielectric, so that the word line will cause conduction between the inversion region and the top diffusion for its associated row, but not for the adjacent row.
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Doering Robert R.
Richardson William F.
Shen Bing W.
Barndt B. Peter
Donaldson Richard L.
Jackson, Jr. Jerome
Kesterson James C.
Texas Instruments Incorporated
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