High performance CMOS word-line driver

Details High performance CMOS word-line driver High performance CMOS word-line driver

1999-12-10

2001-05-22

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

Reexamination Certificate

active

06236617

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is that of DRAM circuits, in particular circuits for driving the signals that activate a DRAM cell in a negative wordline configuration.
BACKGROUND OF THE INVENTION
The negative word line technique, in which the gate of the transfer transistor in a DRAM cell is maintained at a bias voltage below ground (V
ss
) is commonly used to increase retention time by reducing leakage through the transfer transistor.
When this is done, the voltage swing on the wordline driver circuit is increased, as there is now a greater voltage swing (from V
ss
to the boosted driver voltage V
pp
) than was the case when the low bias voltage is at ground, and there is greater voltage stress on the devices in the driver circuit and therefore decreased reliability.
The art has addressed this situation by placing a buffer nfet in series in the driver output stage, by increasing the thickness of the gate oxide in the driver pfet and by increasing the channel length on the devices. These approaches impose extra cost on the circuit.
In one example, shown in “Offset Word-Line Architecture for Scaling DRAMs to the Gigabit Level”, in the IEEE Journal of Solid State Circuits, Vol 23, No. 1, February 1988, the authors propose a scheme for a grounded (not negative) wordline, in which the wordline driver includes a high-threshold pfet and a low-threshold nfet. The result is that the leakage current through the selected wordline is reduced, but the leakage current on all the non-selected wordlines is increased, so that the total leakage from the circuit during standby will be unacceptably high.
SUMMARY OF THE INVENTION
The invention relates to a wordline driver circuit (and associated circuits for supplying the wordline voltage and for selecting the wordline driver circuit) for a memory array that has a higher than normal leakage output stage, is driven by a decoder circuit with a reduced voltage swing, and has a power supply voltage also having a reduced voltage swing. The number of transistors subject to voltage stress is reduced and the area consumed by the circuit is reduced. The active power required to operate a driver according to the invention is reduced because of the reduced voltage swing.
A feature of the invention is the use of inverters with a pfet having a higher than normal threshold, so that leakage current in the group of unselected drivers exposed to the wordline high voltage is reduced.
Another feature of the invention is a reduction in the number of buffer nfets required to avoid hot-carrier problems, thereby saving space.


REFERENCES:
patent: 5712823 (1998-01-01), Gillingham
patent: 5940343 (1999-08-01), Cha et al.
patent: 6049503 (2000-04-01), Khang

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