High performance CMOS pseudo dynamic bit comparator with...

Details High performance CMOS pseudo dynamic bit comparator with... High performance CMOS pseudo dynamic bit comparator with...

2000-07-26

2002-06-04

Lam, Tuan T. (Department: 2816)

Communications: electrical

Digital comparator systems

C326S052000

Reexamination Certificate

active

06400257

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to high performance CMOS comparators, and particularly to one which integrates a bypass function for improve performance.
TRADEMARKS
S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
BACKGROUND
High speed CMOS circuits perform a wide bit compare function. A high performance comparator is needed for VLSI logic and memory applications which enables fast path delay and hence improves cycle time as needed in a microprocessor system. This is particularly important for wide bit comparators with very wide data widths (data widths in excess of 30 bits, sometimes as high as 40 to 50 bits). These comparators could easily consume 30-40% of total critical path delay budget of a computer system.
In existing practice, two comparator implementations are commonly known:
1.) Static comparators performance is limited by static circuits.
2.) Dynamic comparators disadvantage is in their dynamic circuit timing complexity.
In today's VLSI logic and memory applications, it is a difficult task to design high speed wide bit comparators (data width in excess of 30 bits). These comparators need to be extremely fast since they can consume 30-40% of critical path delay budget of a microprocessor system.
SUMMARY OF THE INVENTION
In accordance with our invention we provide a high performance CMOS comparator circuit with a bypass allowing comparing first and second data sets (A & B) with a high data width (more than 30 and illustrated as 48 bits). In many cases, it is often required to compare not only sets A&B but also set A with an additional bypass set, and the preferred circuit embodiment permits this to be achieved.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.


REFERENCES:
patent: 5357236 (1994-10-01), McClure
patent: 5900013 (1999-05-01), Narayan et al.
patent: 5986538 (1999-11-01), Yoon
patent: 6014074 (2000-01-01), Park
patent: 6255856 (2001-07-01), Oh

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