High-performance, CMOS latch for improved reliability

Details High-performance, CMOS latch for improved reliability High-performance, CMOS latch for improved reliability

1987-11-02

1989-01-24

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 3075722, 307585, 365156, G11C 1140

Patent

active

048003000

ABSTRACT:
A CMOS latch circuit is provided which eliminates the lowering of a high voltage level from a precharge/discharge data bus line caused by charge-sharing effect. The CMOS latch circuit is formed of a P-channel precharge transistor (P1), a P-channel drive transistor (P2), an N-channel drive transistor (N1), an N-channel enable transistor (N2), and a transimission gate (TG) for loading a complementary data input signal to a storage node (A) in response to true and complementary load signals. The latch circuit further includes output transistor devices formed of a pair of P-channel output transistors (P3, P4) and a pair of N-channel output transistors (N3, N4) which are all connected in series, and are responsive to true and complementary load signals and to true and complementary data output signals for maintaining the latch circuit in one of two states.

REFERENCES:
patent: 4251739 (1981-02-01), Morozumi
patent: 4506167 (1985-03-01), Little et al.
patent: 4617480 (1986-10-01), Au
patent: 4629909 (1986-12-01), Cameron

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