High performance chip carrier substrate

Details High performance chip carrier substrate High performance chip carrier substrate

2007-01-09

2008-11-25

Norris, Jeremy C (Department: 2841)

Metal working

Method of mechanical manufacture

Electrical device making

C029S849000

Reexamination Certificate

active

07454833

ABSTRACT:
A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.

REFERENCES:
patent: 6172305 (2001-01-01), Tanahashi
patent: 6351393 (2002-02-01), Kresge et al.
patent: 6373717 (2002-04-01), Downes, Jr. et al.
patent: 6487088 (2002-11-01), Asai et al.
patent: 6518516 (2003-02-01), Blackwell et al.
patent: 6538213 (2003-03-01), Carden et al.
patent: 6744067 (2004-06-01), Farnworth et al.
patent: 2002/0060318 (2002-05-01), Katz
patent: 2003/0047352 (2003-03-01), Bhatia et al.
patent: 2004/0188819 (2004-09-01), Farnworth et al.

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