High performance carry chain with reduced macrocell logic...

Details High performance carry chain with reduced macrocell logic... High performance carry chain with reduced macrocell logic...

2006-01-24

2006-01-24

Chaki, Kakli (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S707000, C708S710000

Reexamination Certificate

active

06990508

ABSTRACT:
A programmable logic block in an integrated circuit comprising a plurality of macrocells, an AND-array, an OR-array, and a logic circuit. The plurality of macrocells may comprise logic that may be configured to (i) generate and propagate an inverted carry-input signal and (ii) generate a sum bit. The AND-array may comprise at least two product terms per macrocell. The OR-array may be configured to generate a sum-of-products term for each macrocell in response to the two product terms. The logic circuit may be configured to (a) receive (i) the product terms and (ii) the carry-input signal generated by a first macrocell of the plurality of macrocells and (b) generate (i) a block carry-propagate signal, (ii) a block carry-generate signal, and (iii) a block carry-output signal.

REFERENCES:
patent: 3925652 (1975-12-01), Miller
patent: 4323981 (1982-04-01), Nakamura
patent: 4584661 (1986-04-01), Grundland
patent: 4761760 (1988-08-01), Tomoji
patent: 5084835 (1992-01-01), Okamoto
patent: 5434810 (1995-07-01), Goto et al.
patent: 5481206 (1996-01-01), New et al.
patent: 5701504 (1997-12-01), Timko
patent: 5898602 (1999-04-01), Rothman et al.
patent: 6012079 (2000-01-01), Song
patent: 6034546 (2000-03-01), Jones et al.
patent: 6188240 (2001-02-01), Nakaya
patent: 6201409 (2001-03-01), Jones et al.
patent: 6269386 (2001-07-01), Siers et al.
patent: 6708190 (2004-03-01), Jones et al.
patent: 2001/0037349 (2001-11-01), Hayakawa
Chang et al. , Carry-select adder using single ripple-carry adder, Oct. 29th 1998, IEEE, vol. 34 No. 22 pp. 2101-2103.
Roger Bettman et al., “Reduced Product Term Carry Chain”, U.S. Appl. No. 09/587,708, filed Jun. 5, 2000.

Affiliated with

Also associated with

Rating

High performance carry chain with reduced macrocell logic... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High performance carry chain with reduced macrocell logic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance carry chain with reduced macrocell logic... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3599509