Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-01-31
2003-07-15
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C326S060000, C375S214000
Reexamination Certificate
active
06593867
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data communications. More specifically, the present invention relates to parallel data bus interfaces.
2. Description of the Related Art
Digital signaling plays dominant role in modern computer and electronics products. Computers, microprocessors, DSP and microcontrollers are used in a vast array of consumer, commercial, and government applications. Devices such as kitchen appliances and children's toys now routinely utilize computers. Obviously, the use of personal computers has become commonplace. Computers are used in automotive and commercial applications as well. As shared aspect of virtually all computer applications is the need for computers, processors, microprocessors and microcontrollers to communicate digital information within the devices themselves, as well as to peripheral devices. Peripheral devices include other computers, memory, input/output controllers, DSP's, multi-function peripherals, mass storage devices, printers, network devices and a host of other interface devices.
The preferred means of communicating digital information among and between computers and peripherals is the digital data bus. This type of bus is the standard because of its simplicity and its ability to convey a large amount of data simultaneously, by virtue of the parallel communications paths inherent is such a bus. In addition to the data bus, digital buses are used for addressing and control as well. Parallel digital buses are used for communications within integrated devices, such as personal computers, as well as communications with external peripheral devices.
The simplicity of the parallel digital bus does impose certain limitations and problems. Each bus requires that a large number of circuit conductors be deployed to accomplish the desired interconnections. A large number of conductors require a proportionally large amount of printed circuit board area, or ‘real estate’. Similarly, if cabling is utilized, the cables must also comprise a large number of circuit conductors to implement a parallel digital bus. Of course, the interface connectors become large and more cumbersome. There is an obvious cost penalty associated with the foregoing as well, including larger printed circuit boards, or boards with a greater number of conductive layers. Also, bigger and more expensive cables and connectors. Another aspect of parallel data bus interfaces is the electrical characteristics. Parallel conductors are prone to EMI and cross talk. This can degrade system performance, especially in environments where system performance is being pushed to the limits of modern design. Also, the longer the cable run, the more likely electrical problems are to occur. Distributed impedances grow in magnitude as cabling run lengths increase. Digital square-wave pulses become distorted and signaling reliability goes down.
The market trends in computer technology of all kinds are pushing for faster and smaller devices. Higher reliability continues to be an important goal in systems design. Digital buses become wider as more parallel data paths are needed to meet system performance requirements. Printed circuit board trace routings are pushed ever closer together, exacerbating electrical and propagation issues. Thus there is a need in the art for a high performance digital parallel bus interface and interconnection scheme to mitigate the foregoing issues.
SUMMARY OF THE INVENTION
The need in the art is addressed by the apparatus and methods taught in the present invention. In a first embodiment, a data encoder for combining several data lines into a single medium is taught. The encoder comprises a plurality of signal converters, each having an input for receiving one of a plurality of binary signals, and an output for outputting a discrete amplitude level when the received binary signal is active. Also, an amplitude adder having a plurality of inputs coupled to the outputs of the plurality of signal converters, and an output for outputting an encoded signal according to the sum of the input amplitudes. In a refinement of this invention, the plurality of binary signals includes a clock signal, and the decoder further comprises a clock interface coupled to the amplitude adder and operative to receive the clock signal and gate the output of the amplitude adder in accordance therewith. In one embodiment, the plurality of binary signals are structured as a digital bus.
At a higher level of integration, all of the elements are disposed within an integrated circuit and the amplitude adder output couples to an external connection of the integrated circuit. In a further refinement, output discrete amplitude levels of the plurality of signal converters are related by binary orders of magnitude. The invention may also comprise a low pass filter, having an input coupled to the output of the amplitude adder, and an output for outputting the encoded signal with reduced bandwidth.
An alternative embodiment is taught, which comprises a sinusoidal signal source, a plurality of gain stages, each having an input coupled to the sinusoidal signal source, an output, and a discrete gain value. Also, an analog multiplexer having a plurality of inputs coupled to the outputs of the plurality of gain stages, and a plurality of control inputs coupled to a data bus, and an output for outputting the signal present on a selected one of the plurality inputs according to the present state of the data bus. In a refinement of this invention, the data bus includes a clock signal, and further comprises a clock interface coupled to the analog multiplexer and operative to receive the clock signal and gate the output of the analog multiplexer in accordance therewith. In another refinement, all of the elements are disposed within an integrated circuit and the analog multiplexer output couples to an external connection of the integrated circuit. In another refinement, the discrete gain values are related by binary orders of magnitude. In another refinement, the encoder further comprises a low pass filter having an input coupled to the output of the analog multiplexer, and an output.
In addition to the encoder, the present invention also teaches a data decoder. The data decoder comprises an amplitude discriminator having an input for receiving an amplitude encoded signal, and a plurality of outputs, each activated according to a discrete amplitude level. Also, a symbol generator having a plurality of inputs coupled to the plurality of outputs of the amplitude discriminator, and a plurality of outputs for outputting a predetermined binary symbol according to which of the plurality of inputs receives an active signal. In a refinement of this invention, the amplitude encoded signal includes a sequence of discrete amplitude levels, and it further comprises a clock recovery circuit coupled to the amplitude encoded signal and operable to output a clock signal in synchronous with the sequence of discrete amplitude levels. The clock signal is further coupled to the symbol generator and operable to gate the plurality of outputs in accordance therewith.
In a refinement of the data decoder, the plurality of outputs are structured as a digital bus. In a further refinement, all of the elements are disposed within an integrated circuit and the amplitude discriminator input couples to an external connection of the integrated circuit.
The present invention also teaches several methods of implementing the inventive concepts taught herein. The first is a method of encoding a plurality of data signals into an encoded signal. It comprising the steps of generating a plurality amplitude levels discretely corresponding to the plurality of data signals, and summing the plurality of amplitude levels to produce an amplitude encoded signal. In a refinement of the foregoing, the plurality of binary signals includes a clock signal, and the method further comprises the step of synchronizing a sequence of amplitude encoded signals in accordance with the clock signal. In a further refin
Jeanglaude Jean Bruner
Nguyen Linh T.
Nguyen, P.C.
VDV Media Technologies, Inc.
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