High performance bus driving/receiving circuits, systems and met

Details High performance bus driving/receiving circuits, systems and met High performance bus driving/receiving circuits, systems and met

1995-05-04

1997-09-02

Bocure, Tesfaldet

Pulse or digital communications

Cable systems and components

327 74, 370284, H04L 2700

Patent

active

056639848

ABSTRACT:
Circuitry 200 is provided for transmitting data between a first endpoint and a second endpoint and includes an information line 201 and a dummy line 205. Information transmission circuitry 202, 203, 204 is disposed at the first endpoint for transmitting information on information line 201, transmission circuitry 202, 203, 204 pulling information line 201 to a low voltage during transmission of information of a first logic state and charging information line 201 to a higher voltage during transmission of information of a second logic state. Charging circuitry 206, 207, 208 is disposed at the first endpoint for charging dummy line 205 to a reference voltage during transmission of information on information line 201, charging circuitry 206, 207, 208 charging dummy line 205 at a rate different from a rate at which transmission circuitry 202, 203, 204 charges information line 201 during transmission of information of the second logic state. Receiving circuitry 209 is disposed at the second endpoint for detecting a voltage difference between information line 201 and dummy line 205 and in response determining the logic state of transmitted data on information line 201.

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