High performance bubble chip architecture

Details High performance bubble chip architecture High performance bubble chip architecture

1981-06-30

1983-05-31

Moffitt, James W.

Static information storage and retrieval

Magnetic bubbles

Generators

365 15, G11C 1908

Patent

active

043864171

ABSTRACT:
A major/minor loop bubble memory system architecture includes a passive replicator in the major loop read channel which is connected by a first path to a mode switch-annihilator and a merge point in the major loop write channel and by a second path to an off-chip decision-making means and the merge point in the write channel. The decision-making means is positioned the same or fewer propagation steps than the mode switch-annihilator is from the replicator. The decision making means is activated to cause either the replicated data to pass through the mode switch-annihilator into the write channel or the replicated data to be annihilated in the mode switch-annihilator and the data from a generator to pass into the write channel.

REFERENCES:
patent: 3618054 (1971-11-01), Bonyhard
patent: 3838407 (1974-09-01), Julliussen
patent: 3999172 (1976-12-01), Bhandarkar
patent: 4081861 (1978-03-01), Linn
patent: 4090251 (1978-05-01), Flannigan et al.
patent: 4125875 (1978-11-01), Saito

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