Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure
Reexamination Certificate
2002-02-04
2003-03-04
Nguyen, Tuan H. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
C257S586000, C257S588000
Reexamination Certificate
active
06528861
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to bipolar transistors and, in particular, to a bipolar transistor having an ultra-small, self-aligned polysilicon emitter and an active base region formed utilizing deposition of a blanket silicon-germanium (SiGe) film that is self-aligned to the base window.
2. Description of the Related Art
A bipolar transistor is a three-terminal device that can, when properly biased, controllably vary the magnitude of the current that flows between two of the terminals. The three terminals include a base terminal, a collector terminal and an emitter terminal. The charge carriers, which form the current, flow between the collector and the emitter terminals, while variations in the voltage on the base terminal cause the magnitude of the current to vary.
Due to the increasing demand for battery-powered devices, there is a need for a bipolar transistor that utilizes less power. Lower power consumption can be obtained by reducing the maximum current that can flow between the two terminals. One approach for reducing the maximum current is to reduce the size of the base-to-emitter junction, preferably to sub-lithographic feature sizes.
FIG. 1
shows a portion of a prior-art bipolar transistor
100
that has a base-to-emitter junction with a sub-lithographic width. As shown in
FIG. 1
, transistor
100
includes a collector layer
110
, a base layer
112
that is formed on the collector layer
110
, and a field oxide region FOX that adjoins layer
112
. In addition, transistor
100
includes a thin oxide layer
114
that is formed on a portion of base layer
112
and the field oxide region FOX, and an n+ extrinsic emitter
116
that is formed on the thin oxide layer
114
.
Transistor
100
additionally includes a base silicide contact
122
that is formed on base layer
112
and an emitter silicide contact
124
that is formed on extrinsic emitter
116
. In addition, an oxide spacer
126
is formed on base layer
112
between poly ridge
120
and base contact
122
.
During fabrication, poly ridge
120
is formed to have a maximum width (measured laterally) that is smaller than the minimum feature size that is obtainable with a give photolithographic process. After poly ridge
120
has been formed, emitter region
118
is formed during an annealing step that causes dopants to outdiffuse from poly ridge
120
into base layer
112
. As a result, a very small base-to-emitter junction results. A small base-to-emitter junction limits the magnitude of the current that can flow through transistor
100
. Reducing current, in turn, provides low-power operation.
(See “Poly Emitter Transistor (PRET): Simple Low Power Option to a Bipolar Process,” Wim van der Wel, et al., IEDM 93-453, 1993, pp. 17.6.1-17.6.4.)
One drawback associated with bipolar transistor
100
, however, is that it requires the added cost and complexity of a double polysilicon process (extrinsic emitter
116
is formed from a first polysilicon (poly-1) layer, while poly ridge
120
is formed from a second polysilicon (poly-2) layer.) In addition, emitter dopant diffusion into base
112
can be less, compared to a conventional single-poly device architecture, due to the possible presence of oxide at the poly 1-to-poly 2 interface (emitter
116
to poly ridge
120
interface).
Another drawback of transistor
100
is that, although
FIG. 1
shows oxide spacer
126
formed on poly ridge
120
, in actual practice, it is difficult to form an oxide sidewall spacer on a sloped surface. Gaps can result which, in turn, can lead to an electrical short circuit between base layer
112
and extrinsic emitter
116
following the silicidation process (the process that forms base silicide contact
122
and emitter silicide contact
124
.). Silicide is not formed on oxide. Thus, it is critical that a uniformly thick layer of oxide (space
126
) separate base layer
112
from extrinsic emitter
116
.
A further drawback of transistor
100
is that the slope of the end wall of extrinsic emitter
116
can effect the width of poly ridge
120
. Although
FIG. 1
shows extrinsic emitter
116
with a vertical end wall, in actual practice, the end wall is often non-vertical and non-uniform across a wafer that has a number of bipolar transistors having varying performances.
An additional drawback of transistor
100
is that poly ridge
120
is formed around and in contact with each sidewall of extrinsic emitter
116
. A plan view of extrinsic emitter
116
would show emitter
116
with a square or rectangle shape with poly ridge
120
surrounding emitter
116
. As a result, transistor
100
has a large base-to-emitter contact area and a high base-to-emitter capacitance.
Thus, there is a need for a low-power bipolar transistor with a sub-lithographic base-to-emitter junction that reduces, or preferably eliminates, the previously-described drawback.
U.S. patent application Ser. No. 09/881,904, filed on Jun. 15, 2001 (the same day as the above-referenced provisional application from which this application claims priority), and titled “Bipolar Transistor Width Ultra Small Self-Aligned Polysilicon Emitter and Method of Forming the Transistor,” discloses a bipolar transistor that is formed with a single polysilicon process, and has a substantially vertical end wall. The vertical end wall allows a standard oxide side-wall spacer to be formed adjacent to the extrinsic emitter, thereby reducing the likelihood of any base-to-emitter short circuits.
In addition, the bipolar transistor disclosed in the above-cited application provides a sub-lithographic emitter region that reduces the maximum current that can flow through the transistor, thereby reducing the power consumption and also reducing the base-to-emitter capacitance by limiting the base-to-emitter contact area.
The disclosed bipolar transistor is formed on a wafer that has a buried layer, an epitaxial layer of a first conductivity type that is formed over the buried layer, and an intrinsic base region of a second conductivity type that is formed in the epitaxial layer. The epitaxial layer has a smaller dopant concentration than the buried layer. An isolation region is formed on the surface of the intrinsic region. The transistor also has an extrinsic emitter region that is formed on the isolation region and the extrinsic base region. The sidewall of the extrinsic emitter region is substantially aligned with the sidewall of the isolation region. In addition, the region of the extrinsic emitter that contacts the intrinsic base has a sub-lithographic feature size. An intrinsic emitter region is formed in the intrinsic base region. The intrinsic emitter region contacts the extrinsic emitter region. The transistor additionally has an isolation spacer that is formed on the intrinsic base region to contact the extrinsic emitter.
FIG. 2
shows a portion of the disclosed low-power bipolar transistor
200
. As shown in
FIG. 2
, transistor
200
is formed on a wafer that has an n+ buried layer
210
, and n− epitaxial layer
212
that is formed over n_ buried layer
210
, and a field oxide region FOX that adjoins layer
212
N+ buried layer
210
and n− epitaxial
212
form the collector of transistor
200
. Transistor
200
includes a p− intrinsic base
216
that is formed in n− epitaxial layer
212
. In addition, transistor
200
includes an n+intrinsic emitter region
220
that is formed in p− intrinsic base
216
, and a layer of isolation material
222
that is formed on intrinsic base
216
and the field oxide region FOX. Transistor
200
further includes and extrinsic emitter
224
that is formed on isolation layer
222
, and an oxide spacer
226
that is formed on base
216
adjacent to extrinsic emitter
224
. Transistor
200
also includes a base silicide layer
228
that is formed on base
216
, and an emitter silicide layer
230
that is formed on extrinsic emitter
224
. Isolation layer
222
and extrinsic emitter
224
in the present invention are formed to have substantially aligned si
National Semiconductor Corporation
Stallman & Pollock LLP
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