High performance and reduced area architecture for a fully...

Details High performance and reduced area architecture for a fully... High performance and reduced area architecture for a fully...

2007-01-30

2007-01-30

Phung, Anh (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S168000

Reexamination Certificate

active

11242183

ABSTRACT:
A technique to enhance performance and reduce silicon area for a TCAM system which includes a plurality of CAM blocks that are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of TCAM cells and associated read/write bit lines connecting the group of CAM cells to search bit lines. Each TCAM cell in the TCAM architecture includes a pair of memory elements that is connected to a pair of associated compare circuits such that the interconnections between the memory elements and the compare circuits are substantially vertical in active MOS layers and substantially horizontal in the metal layers to facilitate sharing of adjacent cells thereby providing reduced silicon area and a short aspect ratio.

REFERENCES:
patent: 6678184 (2004-01-01), Lysinger et al.
patent: 6807077 (2004-10-01), Noda et al.
patent: 6900999 (2005-05-01), Yen et al.
patent: 7110275 (2006-09-01), Park

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