High performance and low area write precharge technique for...

Details High performance and low area write precharge technique for... High performance and low area write precharge technique for...

2007-10-02

2007-10-02

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S185230, C365S189011

Reexamination Certificate

active

11280488

ABSTRACT:
A technique to pre-charge a CAM block array that includes a plurality of CAM blocks that is organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to a write/search driver and one or more precharge circuits. In one example embodiment, this is accomplished by precharging each read/write bit line substantially after completing a read cycle using the one or more precharge circuits. Then, precharging each read/write bit line substantially after completing a write cycle using a write/search bit line decoder and driver circuit, followed by precharging each search bit line in the CAM block array using the write/search bit line decoder and driver circuit substantially after completing a search operation.

REFERENCES:
patent: 6845025 (2005-01-01), Nataraj
patent: 7002822 (2006-02-01), Kang et al.

Affiliated with

Also associated with

Rating

High performance and low area write precharge technique for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High performance and low area write precharge technique for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance and low area write precharge technique for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3833896