High-performance address buffer for random-access memory

Details High-performance address buffer for random-access memory High-performance address buffer for random-access memory

1978-09-22

1980-07-22

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307205, 307279, 307350, 307DIG1, 365230, H03K 502, H03K 3353, G11C 706, G11C 800

Patent

active

042141753

ABSTRACT:
A high-performance address buffer for use with a dynamic random-access memory is transistor-transistor logic-input compatible, utilizing a time constant on which activation of one output is dependent.

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patent: 4087704 (1978-05-01), Mehta et al.
patent: 4104733 (1978-08-01), Satoh
patent: 4149099 (1979-04-01), Nagami
Foss et al, "should MOS-RAMS be TTL-Compatible, " Electronic Design (pub.), 6/7/76, pp. 144-146.

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