Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2007-03-06
2007-03-06
Chaki, Kakali (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
09967240
ABSTRACT:
An adder for use in summing two binary numbers in an arithmetic logic unit of a processor. The adder includes a sparse carry-merge circuit adapted to generate a first predetermined number of carries and a plurality of intermediate carry generators coupled to the sparse carry merge circuit and adapted to generate a second predetermined number of carry signals. The adder further includes a plurality of conditional sum generators coupled to the intermediate carry generators and to the sparse carry-merge circuit to provide the sum of the two binary numbers. The adder may also include a multiplexer recovery circuit that enables a single rail dynamic implementation of the adder core.
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Krishnamurthy Ram K.
Mathew Sanu K.
Chaki Kakali
Do Chat C.
Intel Corporation
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