High performance active gate drive for IGBTs

Details High performance active gate drive for IGBTs High performance active gate drive for IGBTs

1999-03-25

2001-03-27

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Slope control of leading or trailing edge of rectangular or...

C327S434000, C327S380000, C327S389000

Reexamination Certificate

active

06208185

ABSTRACT:

FIELD OF THE INVENTION
This invention pertains generally to the field of power electronics and particularly to gate drive circuits for semiconductor power switching devices.
BACKGROUND OF THE INVENTION
Insulated gate bipolar transistors (IGBTs) are finding increasing application, particularly in the field of high power converters. In a typical power converter a gate drive circuit is required as an interface between the logic level signals of the modulator and the IGBT power switches. The design of the gate drive circuit can significantly affect the performance of the IGBT or other power semiconductor device. Ideally, the gate drive circuit should switch the IGBT at a high speed while limiting di/dt and dv/dt and associated noise that is generated during the switching transient. At the same time, it is desirable that the gate drive function to minimize switching losses, the peak reverse recovery current stress during turn-on, and the peak over-voltage stress at turn-off. These diverse functional objectives for the gate drive have been difficult to implement in conventional gate drive circuits. Typical conventional IGBT gate drive circuits have employed fixed gate resistors which are selected to suppress switching electromagnetic interference (EMI) to an acceptable level, and to limit the reverse recovery current at turn-on and the over-voltage at turn-off with minimal energy loss. However, because these objectives are to some extent conflicting, the compromises required have led to less than optimal performance. To satisfy the switching stress constraints and to keep EMI at acceptable levels, the required value of the gate resistor must be relatively large, which leads to long switching delays and higher switching losses, a sacrifice in performance that has been necessary to achieve acceptable noise levels and switching stresses.
Several studies have been made of the optimal choice of the values for the turn-off and turn-on gate resistors with an aim to limiting the turn-on di/dt and the turn-off over-voltage and dv/dt. See, e.g., F. Blaabjerg, et al., “An Optimum Drive and Clamp Circuit Design with Controlled Switching for a Snubberless PWM-VSI-IGBT Inverter Leg,” IEEE PESC. Conf. Rec., 1992, pp. 289-297; R. Chokhawala, et al., “Gate Drive Considerations for IGBT Modules,” IEEE IAS Conf. Rec., 1992, pp. 1186-1195. The use of multiple gate resistors to control the over-voltage during turn-off switching transients at over-current levels has also been investigated. H.G. Eckel, et al., “Optimization of the Turn-Off Performance of IGBT at Over-Current and Short-Circuit Current,” EPE Conf. Rec., 1993, pp. 317-322. This study was limited to turn-off operation only, with an indication that it was difficult to obtain optimized switching characteristics between the over-voltage and the turn-off energy loss at nominal current levels. Investigations have been made of the use of a gate circuit with a closed loop high speed operational amplifier to operate the IGBT in the active region at turn-off. A.N. Githiari, et al., “High Performance Gate Drives Utilizing the IGBT in the Active Region,” IEEE PESC Conf. Rec., 1996, pp. 1754-1759. Using this approach, the turn-off dv/dt can be precisely controlled in accordance with the reference voltage command. The problem with this approach is the large switching loss at turn-off and the fact that the circuit cannot easily be extended to turn-on operation under an inductive load switching transient. A technique for reducing the power loss at turn-on by injecting additional current into the gate is discussed in S. Musumeci, et al., “A New Adaptive Driving Technique for High Current Gate Control Devices,” IEEE APEC Conf. Rec., 1994, pp. 480-486. This method uses a phase-lock-loop to determine the instant of current injection into the gate of the device, which can result in poor operation under transient load current conditions. In addition, the update of the control information occurs with one switching period delay, and the total turn-on delay time is still quite large because a fixed gate resistor is used to limit the di/dt during turn-on.
The use of a high performance current source gate drive used in a modular traction converter is described in A. Lindberg, “MACS ICON-IGBT Propulsion System,” EPE Conf. Rec., 1997, pp. 3.492-3.497. The paper by S. Gediga, et al., “High Power IGBT Converters with New Gate Drive and Protection Circuit,” EPE Conf. Rec., 1995, pp. 66-70, reports on the use of a high performance gate drive for high power IGBT converter applications. This gate drive is based on open loop methods for reduced turn-on di/dt operation with predetermined control points. Turn-off is controlled by using closed loop measurement of the collector voltage which is used to limit the over-voltages for the series-connected IGBTs.
SUMMARY OF THE INVENTION
In accordance with the present invention, an active drive circuit for driving high power IGBTs provides optimized switching performance for both turn-on and turn-off and for all operating conditions. The active gate drive circuit incorporates a three-stage action to improve performance characteristics, including reduced delay time at both turn-on and turn-off, reduced turn-on di/dt and reduction of the associated reverse recovery effects, lower tail voltage and thus lower resultant energy loss at turn-on, controlled over-voltage at turn-off, reduced energy loss due to improved dv/dt characteristics at turn-off, and reduced total switching time at both turn-on and turn-off.
For turn-on of the IGBT, the gate drive circuit of the invention includes a means for providing low resistance rapid charging of the gate during a first stage after receipt of the turn-on signal, a means for providing controlled current charging of the gate during a second stage that follows the first stage, and a means for providing rapid low resistance final charging of the gate to a turn-on voltage supply level during a third stage that follows the second stage and for maintaining the turn-on supply voltage level at the gate while the turn-on signal is present. The first stage minimizes the delay time by rapidly charging the IGBT gate with a large gate current. Once the gate voltage has reached the threshold gate voltage level, the second stage is initiated. During the second stage, control of the turn-on di/dt is achieved by a reduced rate of charging of the gate based on control of the current supplied to the gate. The second stage continues until the collector current reaches the load current plus the peak reverse recovery current. The level of current injected into the gate during the second stage is less than that during a comparable period for a conventional gate drive, thus minimizing the effects of the reverse recovery current on the converter system. Finally, in the third stage, the gate is rapidly charged to reduce the tail voltage, thus decreasing the power loss during turn-on.
A gate drive circuit in accordance with the invention for turning off the IGBT includes a means for providing low resistance rapid discharging of the gate during a first stage after receipt of a turn-off signal, a means for providing controlled current discharging of the gate during a second stage that follows the first stage, and a means for providing rapid low resistance final discharging of the gate to a turn-off voltage supply level during a third stage that follows the second stage and for maintaining the turn-off voltage level at the gate while the turn-off signal is present. The first stage may continue until the rising instant of the collector voltage. The rapid discharging during the first stage considerably reduces both the turn-off delay time and the power loss caused by the slow initial rise of the collector voltage encountered with conventional gate drives. The large gate current during the first stage causes the gate voltage to go below the threshold voltage, resulting in a higher dv/dt and a lower power loss. During the second stage, the gate current is reduced and the collector voltage rise causes the gate voltage to charge up bec

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