High output swing comparator stage

Details High output swing comparator stage High output swing comparator stage

2001-11-20

2003-09-09

Tokar, Michael (Department: 2819)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S255000, C330S258000

Reexamination Certificate

active

06617921

ABSTRACT:

TECHNICAL FIELD
The present invention relates to electrical circuits, and more particularly to a circuit and method for providing a high output swing and high gain to an amplification stage with build in common mode feedback for a comparator circuit.
BACKGROUND OF THE INVENTION
Typically, the design of a controlled gain, open loop comparator circuit inherently limits the output swing range. Controlled gain stages are selected due to their inherent common mode feedback. Recently, there has been a development in providing comparator circuits that allows both high gain and high output swing as well as inherent common mode feedback. These match transconductance (width to length ratio, i.e., W/L, where W is the channel width of the transistor and L is the channel length thereof) of transistor devices in order to provide a low offset across process voltage and temperature variations. In order to keep the input referred offset voltage small, the transistors are sized to substantially match transconductances with one another when in the quiescent condition. However, this creates a problem with input capacitance. Since the comparator stages are AC coupled, the input capacitance of a stage creates a capacitive divider between the output of the previous stage and that stage. This capacitive divider reduces the gain and performance of the comparator. Increasing the size of the coupling capacitors slows down the system. Increasing the current in the amplifiers to compensate requires increased power and area. Furthermore, a gain increase in the comparator is irrelevant if the gain is already enough to saturate the output of the stage. The comparator is designed so that the smallest specified input would saturate its output.
Another problem is that comparator stages that have controlled gain and that match transconductances with one another have a fundamental limitation, the output swing. A typical solution is to employ a differential input/output stage that utilizes a pair of diode connected transistors to provide control of the gain. This has the added benefit of eliminating the need for a common mode feedback loop. However, this reduces the output swing of the stage to approximately a diode drop in single ended configurations and two diode drops in differential configurations. In low power, low voltage analog-to-digital converter designs the comparator voltage swing is an important issue. The first stage sets the noise and offset for the entire system. If the input referred offset voltage is large and the gain of the stage is high enough, the output of the comparator may be saturated to the point where the sign of the output voltage is fixed no matter what the input voltage. With increased output swing, the amount of input referred offset needed to saturate the output of the comparator increases proportionally.
FIG. 1
a
illustrates a prior art fixed gain amplification state
10
of a comparator circuit. The stage includes a first differential input INM coupled to a gate of a first nmos input transistor
36
and a second differential input INP coupled to a gate of a second nmos input transistor
37
. The first and second input transistors
36
and
37
have drains coupled to an active load positive feedback circuit portion
14
comprised of pmos transistors
32
and
33
. A first current mirror
12
comprised of pmos transistors
30
,
31
and
32
are coupled to the active load positive feedback portion
14
on a first end and a first differential output OUTM on a second end. The current through transistor
30
is proportional t the sum of the currents through transistors
31
and
32
. A second current mirror
16
comprised of pmos transistors
33
,
34
and
35
are coupled to the active load positive feedback circuit portion
14
on a first end and a second differential output OUTP on a second end. The current through transistor
35
is proportional to the sum of the currents through transistors
33
and
34
. Transistors
30
,
31
,
32
,
33
,
34
and
35
all have sources coupled to VDD.
The first and second input transistors
36
and
37
have sources coupled to one another to form a node V
1
. The sources of the first and second input transistors
36
and
37
are also coupled to a current source portion
22
comprised of nmos transistors
42
and
43
. A second positive feedback portion
20
comprised of nmos transistor
41
has its gate coupled to the second differential output OUTP and its drain coupled to the first differential output OUTM. A first diode connected portion
18
comprised of nmos transistor
40
has its drain and its gate coupled to OUTM. A third positive feedback portion
24
comprised of nmos transistor
44
has its gate coupled to the first differential output OUTM and its drain coupled to the second differential output OUTP. A second diode connected portion
26
comprised of nmos transistor
45
has its drain and its gate coupled to OUTP. Power transistors
38
and
39
are coupled to a power device signal PD and a bias current signal IB, respectively, and provide input bias current and voltage to the current source portion
22
. Transistors
38
,
39
,
40
,
41
,
42
,
43
,
44
and
45
all have sources coupled to VSS.
The main function of the devices
31
and
34
are to set the common mode voltages of nodes V
2
and V
3
. Transistors
31
and
34
are connected as diodes and have a certain set DC current flowing through the transistors
31
and
34
in the quiescent stage. The transistors
31
and
34
also provide enough negative feedback to stabilize the positive feedback of the active load portion
14
. The diode connected transistors
40
and
45
set the quiescent common mode voltage of OUTP and OUTM. During differential mode the diode connected transistors
40
and
45
have the detrimental effect of limiting the output swing to two times a V
t
plus a V
dsat
regardless of the voltage difference across VDD to VSS.
FIG. 1
b
is a graph
48
of voltage versus time illustrating the voltage swing limitation of the differential output (VOUT) of the prior art stage
10
with a given differential input.
In view of the above, it is apparent that there is potential for improvements in the above amplification stage of the prior art device.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a circuit and method are provided to obtain a high output swing and high gain amplification stage with built in common mode feedback for a comparator device. The present circuit and method provides for an improved amplification stage to a comparator circuit without an external feedback loop. The amplification stage exhibits control over output common mode voltage, while also providing approximately rail to rail output swing. The amplification stage provides for differential outputs with low impedance during common mode and high impedance during differential mode by selectively switching out of the circuit the diode connected transistors used for setting the offset voltage during common mode when the circuit is in differential mode.
In one aspect of the invention, the amplification stage of the circuit is provided with a first current mirror transistor coupled between a first differential output and a voltage source and a transistor selectively coupleable as a diode or as a current source. A first switch is disposed between the selectively coupleable transistor's gate and the first differential output and a second switch is disposed between the selectively coupleable transistor's gate and the second differential output. The first and second switches have a first state for setting the selectively coupleable transistor as a diode for selling the common mode bias voltage on its respective differential output and a second state for setting the selectively coupleable transistor as a current source which provides the outputs with high impedance during differential mode.
Thus, according to another aspect of the present invention, a first node is formed between a gate of the first diode coupled transistor and the first switch and a second node is form

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