Amplifiers – With semiconductor amplifying device – Including push-pull amplifier
Reexamination Certificate
2000-04-27
2001-07-17
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including push-pull amplifier
C330S268000, C330S255000
Reexamination Certificate
active
06262633
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of operational amplifier output stages, and particularly to high output current, low distortion, rail-to-rail output stages.
2. Description of the Related Art
The characteristics of an operational amplifier (op amp) are defined with various specifications. Three of these, i.e., maximum output current, quiescent current, and distortion, tend to be interrelated. For example, the quiescent current, i.e., the current drawn from the power supplies when no signal is applied to the op amp, tends to limit the maximum output current, with an increase in maximum output current requiring a corresponding increase in quiescent current. An increase in quiescent current also tends to improve the distortion performance of the op amp, though at the cost of higher power dissipation.
A known op amp output stage is shown in
FIG. 1
, which is a simplified schematic of the output stage of an AD8041 op amp from Analog Devices, Inc. in Norwood, Mass. A drive circuit
10
produces complementary drive signals
12
and
14
to drive a complementary pair of output transistors Q
1
and Q
2
, respectively. Q
1
and Q
2
are connected in series between supply voltages VCC and VEE, with the junction of their collectors serving as the stage's output terminal OUT. Q
1
and Q
2
conduct respective currents I
Q1
and I
Q2
in response to drive signals
12
and
14
, which are summed at the output terminal to produce an output current I
o
.
Drive circuit
10
is arranged to receive differential inputs V+ and V−, and to produce complementary drive signals
12
and
14
in response; i.e., as drive signal
12
pulls down harder on Q
1
's base to increase the current I
Q1
conducted by Q
1
to the output, drive signal
14
also decreases to reduce the current I
Q2
conducted by Q
2
. Similarly, drive circuit
10
manipulates drive signals
12
and
14
so that when I
Q2
is increased, I
Q1
is decreased.
A number of implementations can be employed to obtain the A/B-type behavior from drive circuit
10
, one of which is illustrated in FIG.
1
. Differential inputs V− and V+ are connected to transistors Q
3
and Q
4
, respectively, each of which is connected as an emitter follower. V− and V+ are also connected to transistors Q
5
and Q
6
, which are also connected as emitter followers; Q
3
and Q
4
are of opposite polarity to that of Q
5
and Q
6
. A pair of transistors Q
7
and Q
8
are connected to receive the outputs of emitter follows Q
3
and Q
4
, respectively, and to conduct first and second currents in response. A pair of transistors Q
9
and Q
10
are connected to receive the outputs of emitter follows Q
5
and Q
6
, respectively, and to conduct third and fourth currents in response. A current mirror circuit
16
made from transistors Q
11
and Q
12
is connected to mirror the current conducted by Q
7
to Q
8
, with the difference current between the mirrored current and the Q
8
current being drive signal
14
. Similarly, a current mirror
18
made from transistors Q
13
and Q
14
is connected to mirror the current conducted by Q
9
to Q
10
, with the difference current between the mirrored current and the Q
10
current being drive signal
12
. The emitters of Q
7
and Q
9
are connected together at a junction
20
and the emitters of Q
8
and Q
10
are connected together at a junction
22
. A compensation capacitor is connected between V− and OUT, and a resistor RI is connected between junctions
20
and
22
to improve the stage's stability. A complementary pair of clamp transistors Q
15
and Q
16
are biased with respective bias voltages V
bias1
and V
bias2
to prevent current mirror transistors Q
14
and Q
12
, respectively, from saturating.
The output stage also includes a transistor Q
17
connected between mirror transistor Q
11
and VCC via a resistor R
2
, and a transistor Q
18
connected between mirror transistor Q
13
and VEE via a resistor R
3
. Q
17
/R
2
and Q
18
/R
3
are part of the scheme to bias output transistors Q
1
and Q
2
at the proper quiescent current. The collector currents of Q
17
and Q
18
are mirrored via Q
11
/Q
12
and Q
13
/Q
14
, respectively, to provide known currents through Q
15
and Q
16
. This, along with bias voltages V
bias1
and V
bias2
, and the relative sizes of Q
1
, Q
15
, Q
2
and Q
16
set the output transistors' quiescent operating point.
In operation, when V− drops below V+, the voltages at the bases of Q
7
and Q
9
decrease. This results in the current through Q
7
and Q
10
(via R
1
) to be increased, and that through Q
8
and Q
9
to decrease. The Q
10
current is greater than the mirrored Q
9
current, and the resulting difference current (drive signal
12
) pulls down on the base of output transistor Q
1
, increasing the current IQ. provided to the output terminal. At the same time, the mirrored Q
7
current is greater than the Q
8
current, and the resulting difference current (drive signal
14
) reduces the drive to Q
2
, and thereby reduced I
Q2
. With IQ
1
increased and I
Q2
decreased, the net output current I
out
is increased.
Similarly, when V+ falls below V−, more current flows through the Q
9
/R
1
/Q
8
path, and less flows through the Q
10
/R
1
/Q
7
path, increasing the drive to output transistor Q
2
and reducing it to Q
1
, producing a net reduction in I
o
.
The maximum amount of current from Q
1
is limited by the amount of current conducted by Q
10
, which is in turn limited by the current sources I
4
and I
1
connected in series with follower transistors Q
3
and Q
6
. Specifically, the maximum current from Q
1
is given by the lesser of 1)&bgr;
Q1
*&bgr;
Q10
*I
4
and 2)&bgr;
Q1
*&bgr;
Q7
*I
1
. Similarly, Q
2
is limited by the amount of current conducted by Q
8
, which is limited by the current sources I
2
and I
3
connected in series with follower transistors Q
4
and Q
5
, with the maximum current from Q
2
given by the lesser of 1)&bgr;
Q2
*&bgr;
Q9
*I
3
and 2)&bgr;
Q2
*&bgr;
Q8
*I
2
. Thus, the stage's quiescent current depends on the magnitudes of the I
1
-I
4
currents, along with the relative sizes of several of the transistor' emitters. Increasing I
1
-I
4
increases the maximum value of I
o
, though doing so also increases the stage's quiescent current and power dissipation.
The stage's quiescent current also affects its distortion performance. Some nonlinearity is introduced into the output by the driver stage, primarily due to the behavior of transistors Q
7
-Q
10
as they act to sink and source the required base currents needed by the output transistors. The magnitude of the nonlinearity is directly related to the percentage change of the currents through Q
7
-Q
10
. Increasing the stage's quiescent current lowers this percentage change, which reduces the nonlinearity and thus improves the distortion performance. However, as noted above, increasing quiescent current causes a corresponding and often undesirable increase in power dissipation.
SUMMARY OF THE INVENTION
An op amp output stage is presented which, when compared with prior art output stages, provides lower distortion and up to twice as much output current for the same quiescent current. Alternatively, the new stage provides an output current equivalent to that of a prior art amplifier while reducing quiescent current by up to half.
This improved performance is accomplished by providing one or more additional base drive paths for each of the output transistors of an output stage that otherwise resembles the circuit depicted in FIG.
1
. Several means are described by which this is done. For example, a pair of transistors can be employed to mirror components of the output transistors' drive signals back to their respective output transistors, thereby providing an additional base drive path to each. The additional base drive reduces the demand on the drive signal transistors (Q
7
-Q
10
), which lowers the distortion they might otherwise contribute. Alternatively
Analog Devices Inc.
Choe Henry
Koppel & Jacobs
Pascal Robert
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