Amplifiers – With semiconductor amplifying device – Including push-pull amplifier
Reexamination Certificate
2002-06-19
2004-05-25
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including push-pull amplifier
C330S265000
Reexamination Certificate
active
06741133
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an amplifier for driving a load, and, in particular, it relates to an amplifier that is high-speed, of high output power and stable in varying load.
2. Background Arts
There are cases in which the necessity arises for high-speed and high-electric-power driving of circuit elements that serve as loads in various types of electrical and electronic devices such as circuit element testers. In such cases, push-pull amplifiers, complementary amplifiers or combinations thereof are frequently used as the high output amplifiers which are the final stages in which such driving is performed.
A push-pull amplifier that is constructed using bipolar transistors is described in Japanese Laid-open Publication JP1996-32367A. This push-pull amplifier could show a lower crossover distortion without increasing an idling current (through current) in the output stage and high efficiency. Because any part of the circuit is not cut off there is not accumulation of minority carriers, which may be a problem with bipolar transistors, then, higher speed and broader bands can be achieved.
FIG. 1
shows high output amplifier
10
based on a conventional technology similar to that of the aforementioned push-pull amplifier. The high output amplifier
10
is constructed of circuit elements arranged between supply voltages VD and VS. Load voltage V
2
, which is essentially equal to control voltage V
1
that has been input into terminal
1
, is output to terminal
2
. Transistors Q
1
and Q
2
are biased by a series of bias circuits comprised of resistances R
1
and R
2
and diodes D
1
and D
2
. Terminal
1
is connected to a common connecting point of diodes D
1
and D
2
so that control voltage Vc is input into the control terminals (bases) of transistors Q
1
and Q
2
respectively. Transistors Q
1
and Q
2
are, respectively, NPN and PNP transistors and their emitters are connected to terminal
2
through resistance R
4
or resistance R
5
. Transistors Q
1
and Q
2
act as a complementary buffer. The respective collectors of transistors Q
1
and Q
2
are connected to supply voltages VD and VS through resistances R
3
and R
6
respectively and are also connected to the non-inverting input terminals of amplifiers A
1
and A
2
. Outputs of amplifiers A
1
and A
2
are connected to the gates of respective transistors Q
3
and Q
4
and the inverting input terminals of amplifiers A
1
and A
2
are connected to the sources of the respective transistors Q
3
and Q
4
. Further, the sources of transistors Q
3
and Q
4
, which are field effect transistors (FET), are connected to the respective supply voltages VD and VS through resistances R
7
and R
8
. The drains of transistors Q
3
and Q
4
are both connected to terminal
2
. Load LD is connected to terminal
2
. Load LD may generally be passive or active.
First, we shall consider this amplifier
10
by ignoring transistors Q
3
and Q
4
. Transistors Q
1
and Q
2
act in response to control voltage Vc so as to output voltage V
2
, which is close to control voltage Vc, to load LD. However, when load LD is heavy (when load current
12
is high such as in the case of low load impedance), load voltage V
2
does not follow control voltage Vc. At a setting at which load current I
2
flows out to load LD, transistor Q
1
approaches saturation due to an increase of load current I
2
and transistor Q
2
is cut off. However, load current I
2
also flows to resistance R
3
and voltage is generated across resistance R
3
. Amplifier A
1
controls the gate voltage of transistor Q
3
so that the voltage applied across resistance R
3
and the voltage applied across resistance R
7
become equal to each other. Current of a value obtained by dividing the value of voltage across the resistance R
3
by the value of resistance R
7
is supplied from the drain of transistor Q
3
to the terminal
2
. When this occurs, the current flowing through transistor Q
1
is decreased and the voltage across resistance R
3
is also decreased. By means of this negative feedback, high output amplifier
10
is stabilized when the voltage applied across resistance R
3
reaches a certain level. Similar stabilization also occurs at a setting at which load current I
2
flows in from load LD. Similar actions are also effected on the sides of transistors Q
2
and Q
4
. Consequently, there are two feedback loops of electrical signals. In one loop the signal is fed back from terminal
2
to terminal
2
via the transistor Q
1
, amplifier A
1
and transistor Q
3
and in another loop the signal is fed back from terminal
2
to terminal
2
via the transistor Q
2
, amplifier A
2
and transistor Q
4
. So that any electrical signal on terminal
2
, input to or generated at terminal
2
, which may be a change in voltage or current through originated from a change in voltage, current or circuit parameter, is fed back negatively.
In the amplifier
10
of
FIG. 1
, as indicated above, we have described transistors Q
3
and Q
4
as field effect transistors for high power use. However, they may also be bipolar transistors for high power use and switching-mode power sources. Further, field effect transistors or amplifiers may be used in place of transistors Q
1
and Q
2
. However, transistors Q
1
and Q
2
are generally of comparatively high speed and low power and transistors Q
3
and Q
4
are of comparatively low speed and high power.
When transistors Q
3
and Q
4
are field effect transistors or bipolar transistors as described above, and, in particular, the circuit parameters are set so that the output currents of the transistors do not become completely zero even if the load current is zero. This is performed for the purpose of fast response when the load has suddenly changed. Accordingly, when the load current is zero in this way, the through current that flows through the two transistors is called the design through current.
Where load LD may have various type of impedance (passive or active) the aforementioned negative feedback loop may possibly be changed to a positive feedback loop to cause oscillation. Therefore, capacitors C
1
and C
2
are connected in parallel to resistances R
3
and R
4
and roll-off of the negative feedback loop is effected. When transistors Q
3
and Q
4
are power field effect transistors, the frequency characteristics of these power field effect transistors do not extend over a wide range. Then without capacitors C
1
and C
2
, the actual power field effect transistors can simulate equivalents of wide-band field effect transistors with capacitors C
1
and C
2
.
SUMMARY OF THE INVENTION
Although a structure like that of high output amplifier
10
described above is stable when the load current changes slowly, there is the possibility that a large through current that exceeds the expected design through current will be generated in transistors Q
3
and Q
4
when the load current changes suddenly (quickly). For example, there are cases in which a suitable load resistance is connected and in which the input voltage changes rapidly, i.e., more rapidly than the response speed of the aforementioned negative feedback loop. Further, when high output amplifier
10
is used in the device power source of an integrated circuit (IC) tester, there are cases in which the operating state of an IC that is connected as the load will change due to signals from the outside. For example, when there has been a change from the usual operating state to a standby state, the load current changes more rapidly than the response speed of the aforementioned negative feedback loop of high output amplifier
10
.
In order to clearly understand problems this invention intends to solve, we should consider the case in which load current I
2
flowing into the current source load LD changes alternately and rapidly between 0 and IL. When load current I
2
is IL, said load current I
2
flows out from terminal
2
to the load (current source load).
(a) A steady state in which the load current I
2
is 0: The voltages of terminal
1
and terminal
2
, alt
Akama Hideo
Kinsho Kenji
Agilent Technologie,s Inc.
Mottola Steven J.
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