High/low doping profile for twin well process

Details High/low doping profile for twin well process High/low doping profile for twin well process

1989-10-30

1990-05-29

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 56, 437 57, 437 28, 437 27, 357 42, 357 91, 357 2311, H01L 21265, H01L 2700

Patent

active

049295659

ABSTRACT:
A process for forming n- and p-wells in a semiconductor substrate wherein each well has a shallow, highly-doped surface layer whose depth may be independently controlled. This high/low doping profile for a twin well CMOS process may be produced using only one mask level. The method provides high/low impurity profiles in each well to optimize the NMOS and PMOS active transistors; provides close NMOS to PMOS transistor spacing; avoids a channel-stop mask level and avoids a threshold adjustment/punchthrough mask level.

REFERENCES:
patent: 4295266 (1981-10-01), Hsu
patent: 4409726 (1983-10-01), Shiota
patent: 4434543 (1984-03-01), Schwabe et al.
patent: 4435895 (1984-03-01), Parrillo et al.
patent: 4481705 (1984-11-01), Haskell
patent: 4516316 (1985-05-01), Haskell
patent: 4554726 (1985-11-01), Hillenius et al.
patent: 4684971 (1987-08-01), Payne
patent: 4713329 (1987-12-01), Fang et al.
patent: 4717683 (1988-01-01), Parrillo et al.
patent: 4761384 (1988-08-01), Neppl et al.
patent: 4847213 (1989-07-01), Pfiester
patent: 4868135 (1989-09-01), Ogura et al.

Affiliated with

Also associated with

Rating

High/low doping profile for twin well process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High/low doping profile for twin well process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High/low doping profile for twin well process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-520647