Amplifiers – With semiconductor amplifying device – Including plural stages cascaded
Reexamination Certificate
2001-06-28
2002-05-21
Lee, Benny (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including plural stages cascaded
C330S296000
Reexamination Certificate
active
06392492
ABSTRACT:
FIELD OF INVENTION
The present invention relates to solid state, low noise cascode amplifiers, and particularly to such amplifiers having high linearity.
BACKGROUND OF THE INVENTION
The present invention finds wide application in many forms of low noise amplifiers. One application of the invention is in WCDMA, wide band code division multiplex access, receivers in radio telephone transceivers. One current specification calls for a third order intercept point IIP3 of greater than five dBm. The cascode amplifier architecture is generally preferred in wireless applications. This topology provides excellent input to output isolation. However, in cascode low noise amplifier inherently has a lower IIP3 than single transistor, emitter amplifiers. It is highly desirable to provide excellent linearity in comparison with other cascode low noise amplifiers while maintaining a good noise figure, dynamic range, input/output isolation and minimize return loss.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a cascode low noise amplifier having high linearity while maintaining desirable values of other cascode configured low noise amplifier parameters. It is a further object of the present invention to provide an amplifier of the type described in which gain is maintained while emitter degeneration is utilized.
Briefly stated in accordance with the present invention, emitter generation is employed to improve IIP3 while maintaining gain through bias optimization. Termination for harmonics produced in the circuit is also provided. Consequently, linearity, dynamic range are both maximized. The harmonic termination minimized spurious signals when two tones are provided to the input of low noise amplifier.
REFERENCES:
patent: 3890576 (1975-06-01), Kobayashi
patent: 4250463 (1981-02-01), Foster
patent: 6147559 (2000-11-01), Fong
Larson, L.E., “Integrated Circuit Technology Options for FRIC's-Present Status and Future Directions,” IEEE Journal of Solid-State Circuits, vol. 33, No. 3 Mar. 1988, pp. 387-399.
Blakely , Sokoloff, Taylor & Zafman LLP
Choe Henry
International Business Machines - Corporation
Lee Benny
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