High level synthesis for partial scan testing

Details High level synthesis for partial scan testing High level synthesis for partial scan testing

1993-08-25

1996-04-30

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, 364578, 371 223, G06F 1750

Patent

active

055131182

ABSTRACT:
A method for performing high level synthesis of integrated circuits simultaneously considers testability and resource utilization. The method considers the relationship between hardware sharing, loops in the synthesized data path, and partial scan testing overhead. Hardware sharing is used to minimize the quantity of scan registers required to synthesize data paths with a minimal quantity of loops. A random walk based algorithm is used to break all control data flow graph (CDFG) loops with a minimal quantity of scan registers. Subsequent scheduling and assignment avoids the formation of loops in the data path by reusing the scan registers, while ensuring high resource utilization of the components of hardware costs: execution units, registers and interconnects. The partial scan overhead incurred is less than that of conventional gate level design partial scan techniques.

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